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3-channel clock generator, 24 outputs data sheet AD9531 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features 3 fully integrated pll/vco cores (pll1, pll2, and pll3) jitter performance: 0.462 ps rms typical pll1, fractional-n mode, 12 khz to 20 mhz bandwidth loss of reference and lock detection for each pll pin-configurable common frequency translations automatic synchronization of all outputs on power-up manual output synchronization capability package available in an 88-lead lfcsp pll1 details fractional-n/integer-n modes optional external vcxo fixed delay mode for constant static phase offset 2 reference clock inputs input format: differential/single-ended frequency range: 9.5 mhz to 260 mhz reference switching: manual/automatic 10 ultralow jitter hstl/cmos outputs up to 400 mhz pll2 details integer-n mode (1 reference clock input) input format: differential/single-ended/crystal 1 frequency range: 9.5 mhz to 250 mhz 12 hstl/cmos outputs up to 400 mhz pll3 details integer-n mode (1 reference clock input) frequency range: 9.5 mhz to 100 mhz input format: differential/crystal (supports a 25 mhz to 50 mhz at-cut quartz crystal resonator) 2 hstl/lvds/cmos outputs to 400 mhz/150 mhz (differential/cmos) applications radio equipment controller clocking low jitter/phase noise clock generation and distribution clock generation and translation for sonet, 10ge, 10g fc, and other 10 gbps protocols 40 gbps/100 gbps networking line cards, including sonet, synchronous ethernet, otu2/3/4 forward error correction (g.710) high performance wireless transceivers ate and high performance instrumentation broadband infrastructures ethernet line cards, switches, and routers sata and pci-express general description the AD9531 provides a multioutput clock generator function and three on-chip phase-locked loop (pll) cores with spi programmable output frequencies and formats. pll1 provides two reference inputs and 10 outputs and includes four user selectable loop configurations. the pll has a fully integrated loop filter requiring only a single external capacitor (or a series rc network). pll1 provides a wide range of output frequencies up to 400 mhz and is capable of operating with an external voltage controlled crystal oscillator (vcxo) and loop filter, instead of the integrated voltage controlled oscillator (vco) and loop filter. pll2 is an integer-n pll providing a single reference input and 12 outputs. pll2 synthesizes output frequencies up to 400 mhz from the ref2_x source and synchronizes the output clocks to the input reference. pll3 provides a single reference input and two outputs. pll3 synthesizes output frequencies up to 400 mhz from the ref3_x source and synchronizes the output clocks to input reference. the AD9531 is available in an 88-lead lfcsp and is specified over the ?40c to +85c operating temperature range. throughout this data sheet, multifunction pins, such as lor/m4, are referred to either by the entire pin name or by a single function of the pin (for example, lor, when only that function is relevant). in other cases, the text and figures of this data sheet contain references to a channel rather than a pin. for example, ref_a refers to the ref_a channel rather than the ref_ap and ref_an pins. likewise, out3_1 refers to channel 1 of pll3 rather than the out3_1p and out3_1n pins. additionally, an abbreviated notation for a pin pair replaces an explicit reference to a each pin (for example, ref_ax signifies the ref_an and ref_ap pins.).
AD9531 data sheet table of contents features .............................................................................................. 1 applications ................................................................................... 1 general descript ion ......................................................................... 1 revision history ............................................................................... 3 functional block diagram .............................................................. 4 specifications ..................................................................................... 5 conditions ..................................................................................... 5 supply current .............................................................................. 5 power dissipation ......................................................................... 6 ldet1/m1, ldet2/m2, ldet3/m3, and lor/m4 pins ...... 8 ref1_sel pin ............................................................................... 8 pll1 characteristics .................................................................... 8 pll2 characteristics .................................................................. 13 pll3 characteristics .................................................................. 17 serial control port ..................................................................... 20 absolute maximum ratings .......................................................... 21 esd caution ................................................................................ 21 pin configuration and function descriptions ........................... 22 typical performance characteristics ........................................... 25 pll1 characteristics .................................................................. 25 pll2 characteristics .................................................................. 26 pll3 characteristics .................................................................. 27 general characteristics ............................................................. 28 terminology .................................................................................... 29 theory of operation ...................................................................... 30 pll1 integer/fractional - n pll ............................................ 30 pll1 loop configurations ........................................................ 31 pll1 reference clock inputs (ref1_ax/ref1_bx) ............. 34 pll1 reference frequency scaling .......................................... 34 pll1 phase frequency detector (pfd) and charge pumps ..... 35 pll1 loop filter ......................................................................... 35 pll1 interna l vco .................................................................... 35 pll1 vco divider (m1) ........................................................... 35 pll1 external vcxo input (rfin1_x) .................................. 35 pll1 clock distribution ........................................................... 36 pll1 holdover mode and freerun mode ............................... 37 pll1 reference selection manual and automatic ............. 37 pll1 internal vco calibration ............................................... 38 pll1 - modulator .................................................................. 40 pll1 lock detector ................................................................... 40 pll2 integer - n pll ................................................................ 41 pll2 reference clock input (ref2_p/ref2_n) .................. 41 pll2 reference divider (r2) .................................................... 41 pll2 pfd and charge pump ................................................... 41 pll2 loop filter ......................................................................... 42 pll2 vco ................................................................................... 42 pll2 vco divider (m2) ........................................................... 44 pll2 feedback divider (n2) .................................................... 44 pll2 clock distribution ........................................................... 44 pll3 integer - n pll ................................................................... 46 pll3 refer ence clock input (ref3_p/ref3_n) .................. 46 pll3 input frequency scaling ................................................. 46 pll3 pfd and charge pumps .................................................. 46 pll3 loop filters ....................................................................... 47 pll3 vcos ................................................................................. 47 pll3 feedback dividers ............................................................ 47 pll3b reference divider (r3b) .............................................. 47 pll3 clock distribution ........................................................... 47 additional features ........................................................................ 49 power - on reset (por) ............................................................. 49 rom profiles .............................................................................. 49 multifunction pins (ldet1/m1, ldet2/m2, ldet3/m3, lor/m4) ..................................................................................... 49 loss of reference (lor) ............................................................ 50 pll lock detection (ldetx) .................................................. 51 automatic output synchronization ........................................ 51 serial control port ......................................................................... 54 serial control port pin descriptions ....................................... 54 operation of the serial control port ....................................... 54 instruction word (16 bits) ........................................................ 55 msb/lsb first transfers ........................................................... 55 register map ................................................................................... 57 register map details ...................................................................... 60 serial port control registers register 0x0000 to register 0x0005 .......................................................................................... 60 device identification and rom profile registers register 0x000a to register 0x000e ....................................................... 60 status registers register 0x0080 to register 0x0082 .......... 61 ldet/lor control reg isters register 0x0083 to register 0x0085 .......................................................................................... 61 pll1 registers ............................................................................ 62 rev. 0 | page 2 of 88
data sheet AD9531 rev. 0 | page 3 of 88 pll2 registers ............................................................................. 69 ? pll3 registers ............................................................................. 75 ? rom profile data ............................................................................ 77 ? rom profile 0 to rom profile 15 ............................................ 77 ? rom profile 16 to rom profile 31 .......................................... 78 ? rom profile 32 to rom profile 47 ......................................... 80 ? rom profile 48 to rom profile 63 .......................................... 82 ? thermal performance ..................................................................... 84 ? thermal resistance ..................................................................... 84 ? applications information ............................................................... 85 ? interfacing to the multifunction pins ...................................... 85 ? interfacing to the rfin1_x pins ............................................... 86 ? driving ref2 or ref3 with 3.3 v cmos logic .................... 87 ? using ref2 or ref3 with a crystal resonator ...................... 87 ? outline dimensions ........................................................................ 88 ? ordering guide ............................................................................... 88 ? revision history 1/16revision 0: initial version
AD9531 data sheet functional block dia gram pll1 pll2 d1 a d1c fractiona l pl l integr a ted vco integer pl l integr a ted vco integer pl l integr a ted vco switch over contro l d3 a 3 lock detect pins 4 power-u p profile selects lor (loss of reference) pll3 d1b 4 outputs ref1_ a lor2 rfin AD9531 ref1_b ref1_se l ref2 sdio ref3 sclk cs 4 outputs 2 outputs 2 outputs 3 outputs 3 outputs 4 outputs 1 output 1 output ldet1/m1 ldet2/m2 ldet3/m3 lor/m4 d3b d2 a d2b d2c d2d 3-wire spi inter f ace 12973-001 figure 1. rev. 0 | page 4 of 88
data sheet AD9531 specifications typical values are given for 3.3 v supplies at 3.3 v 5% and 1.8 v supplies at 1.8 v 5%; t a = 25c. minimum and maximum values apply over the full variation of supply voltage and t a (?40c to +85c) as listed in table 1 , unless otherwise specified . conditions table 1 . parameter min typ max unit test conditions/comments supply voltage 3 v supply pins 3.3 v 3.3 v 5% 1.8 v supply pins 1.8 v 1.8 v 5% temperature range, t a ?40 +25 +85 c supply current table 2 . parameter min typ max unit test conditions/comments supply current case 1 pll1 : off; pll2 : off; pll3 : off 1.8 v supply pll1 pins 6 ma pll2 pins 19 ma pll3 pins 1.5 ma dvdd 3 ma 3.3 v supply pll1 pins 3.2 ma pll2 pins 1.3 ma pll3 pins 0.1 ma case 2 pll1: d ifferential input at 12 2.88 mhz, hstl output at 122.88 mhz, all outputs active, int ernal vco; pll2: off; pll3: off 1.8 v supply pll1 pins 270 ma pll2 pins 19 ma pll3 pins 1.5 ma dvdd 0.3 ma 3.3 v supply pll1 pins 34 ma pll2 pins 1.3 ma pll3 pins 0.1 ma case 3 pll1: off; pll2: 3.3 v, cmos input at 50 mhz, hstl output at 156.25 mhz, all outputs active; pll3 : off 1.8 v supply pll1 pins 6 ma pll2 pins 280 ma pll3 pins 1.5 ma dvdd pin 0.3 ma 3.3 v supply pll1 pins 3.2 ma pll2 pins 22 ma pll3 pins 0.1 ma rev. 0 | page 5 of 88
AD9531 data sheet parameter min typ max unit test conditions/comments case 4 pll1: off; pll3: 3.3 v, cmos input at 25 mhz, out3_0 and out3_1 at 125 mhz (1.8 v cmos and hstl, respectively); pll2 : off 1.8 v supply pll1 pins 6 ma pll2 pins 19 ma pll3 pins 72 ma dvdd pin 0.3 ma 3.3 v supply pll1 pins 3.2 ma pll2 pins 1.3 ma pll3 pins 0.1 ma case 5 p ll1: differential input at 122.88 mhz, hstl output at 122.88 mhz, all outputs active, internal vco ; pll2: 3.3 v, cmos input at 50 mhz, hstl output at 156.25 mhz, all outputs active ; pll3: 3.3 v, cmos input at 25 mhz, out3_0 and out3_1 at 125 mhz (1.8 v cmos and hstl, respectively ) 1.8 v supply pll1 pins 270 ma pll2 pins 280 ma pll3 pins 72 ma dvdd pin 0.3 ma 3.3 v supply pll1 pins 34 ma pll2 pins 23 ma pll3 pins 0.1 ma incremental supply current pll1, external vcxo configuration 1.8 v supply (pll1 pins ) ? 22 ma 3.3 v supply (pll1 pins ) ? 27 ma pll3, dual loop configuration 1.8 v supply (pll3 pins ) 36 ma 3.3 v supply (pll3 pins ) 0 ma power dissipation table 3 . parameter min typ max unit test conditions/comments power consumption does not include power dissipated in the external resistors case 1 pll1: off; pll2: off; pll3 off 1.8 v supply pll1 pins 11 mw pll2 pins 35 mw pll3 pins 2.5 mw dvdd pin 0.5 mw 3.3 v supply pll1 pins 11 mw pll2 pins 4.0 mw pll3 pins 0.3 mw rev. 0 | page 6 of 88
data sheet AD9531 parameter min typ max unit test conditions/comments case 2 pll1: d ifferential input at 122.88 mhz, hstl output at 122.88 mhz, all outputs active, internal vco; pll2: off; pll3: off 1.8 v supply pll1 pins 480 mw pll2 pins 35 mw pll3 pins 2.5 mw dvdd pins 0.5 mw 3.3 v supply pll1 pins 112 mw pll2 pins 4.0 mw pll3 pins 0.3 mw case 3 pll1: off; pll2: 3.3 v, cmos input at 50 mhz, hstl output at 156.25 mhz, all outputs active; pll3 : off 1.8 v supply pll1 pins 11 mw pll2 pins 500 mw pll3 pins 2.5 mw dvdd pins 0.5 mw 3.3 v supply pll1 pins 11 mw pll2 pins 73 mw pll3 pins 0.3 mw case 4 pll1: off; pll2 : off ; pll3: 3.3 v, cmos input at 25 mhz, out3_0 and out3_1 at 125 mhz (1.8 v cmos and hstl, respectively) 1.8 v supply pll1 pins 11 mw pll2 pins 35 mw pll3 pins 130 mw dvdd pins 0.5 3.3 v supply pll1 pins 11 mw pll2 pins 4.0 mw pll3 pins 0.3 mw case 5 pll1: differential input at 122.88 mhz, hstl output at 122.88 mhz, all outputs a ctive, internal vco ; pll2: 3.3 v, cmos input at 50 mhz, hstl output at 156.25 mhz, all outputs active; pll3: 3.3 v, cmos input at 2 5 mhz, out3_0 and out3_1 at 125 mhz (1.8 v cmos and hstl, respectively) 1.8 v supply pll1 pins 480 mw pll2 pins 500 mw pll3 pins 130 mw dvdd pins 0.5 mw 3.3 v supply pll1 pins 112 mw pll2 pins 73 mw pll3 pins 0.3 mw incremental power consumpton change in power consumption when a specific circuit block or function is made active (or inactive) pll1, external vcxo configuration 1.8 v supply (pll1 pins) ?39 mw 3.3 v supply (pll1 pins) ?89 mw rev. 0 | page 7 of 88
AD9531 data sheet rev. 0 | page 8 of 88 parameter min typ max unit test conditions/comments pll3, dual loop configuration mw 1.8 v supply (pll3 pins) 65 mw 3.3 v supply (pll3 pins) 0 mw ldet1/m1, ldet2/m2, ldet 3/m3, and lor/m4 pins in addition to the lor/m4 pin, a secondary lor indicator pin is possible via out3_0 (see the out3_0 driver section). table 4. parameter min typ max unit test conditions/comments output specifications load current: 1 ma 1.8 v operating mode the 3.3 v mode bit in regist er 0x0083 or register 0x0084 is logic 0 for the associated pin output voltage high v dd ? 0.2 v relative to the supply pins (pin 49, pin 78, pin 61, and pin 6) for ldet1/m1, ldet2/m2, ldet3/m3, and lor/m4, respectively low 0.2 v 3.3 v operating mode the 3.3 v mode bit in register 0x0083 or register 0x0084 is logic 1 for the associated pin output voltage high 2.7 v low 0.2 v input specifications applies during a power-on/reset sequence (see the power-on reset (por) section and the multifunction pins (ldet1/m1, ldet2/m2, ldet3/m3, lor/m4) section) input high voltage (v ih ) 1.2 v input low voltage (v il ) 0.7 v external resistive load 3 10 100 k required termination to ground or 1.8 v for logic 0 or logic 1, respectively input capacitance (c in ) 3 pf ref1_sel pin table 5. parameter min typ max unit test conditions/comments input specifications input high voltage (v ih ) 1.4 v input low voltage (v il ) 1.0 v input current (i inh , i inl ) ?2 +2 a input capacitance (c in ) 3 pf pll1 characteristics pll1 reference inputs (ref1_a and ref1_b) table 6. parameter min typ max unit test conditions/comments differential mode capacitive coupling required input frequency range 2 frequency multiplier bypassed 9.5 260 mhz enabled 9.5 100 mhz input sensitivity 200 mv p-p input slew rate 100 v/s minimum limit imposed for jitter performance
data sheet AD9531 rev. 0 | page 9 of 88 parameter min typ max unit test conditions/comments common-mode internally generated bias voltage 1.0 v hysteresis 20 mv differential input resistance 19 k differential input capacitance 3 pf duty cycle 40 60 % required for input frequencies below 20 mhz; limited by spurious performance when 2 frequency multiplier is in use cmos mode single-ended input single-ended operation is only applicable to the ref1_ap and ref1_bp pins; for both of these inputs, the 2.5 v or 3.3 v mode is selectable via register 0x0103 input frequency range 2 frequency multiplier bypassed 9.5 260 mhz enabled 9.5 100 mhz hysteresis 430 mv input resistance 46 k input capacitance 3 pf duty cycle 40 60 % required for input frequencies below 20 mhz; limited by spurious performance when 2 frequency multiplier is in use. 3.3 v operating mode input voltage bias 1.65 v 50% of 3.3 v supply, pin 23 (vdd1_3v3) high 2.0 v low 1.3 v 2.5 v operating mode input voltage bias 1.25 v 38% of 3.3 v supply, pin 23 (vdd1_3v3) high 1.5 v low 0.9 v pll1 distribution clock outputs (out1_0x to out1_9x) table 7. parameter min typ max unit test conditions/comments hstl mode specifications assume a 100 termination across the differential output pins output frequency 400 mhz rise/fall time (20% to 80%) 120 170 ps listed values are for the edge (rising or falling) with the lesser rate of change (|v/t|) duty cycle up to f out = 400 mhz 45 50 55 % differential output voltage swing 950 mv magnitude of voltage across pins; output driver static common-mode output voltage 870 mv output driver static cmos mode output frequency 150 mhz 10 pf load rise/fall time (20% to 80%) 1.0 ns 10 pf load; listed value is for the edge (rising or falling) with the lesser rate of change (|v/t|) duty cycle 50 % 10 pf load output voltage high (v oh ) v dd ? 0.2 v relative to the vdd1_03, vdd1_47, and vdd1_89 pins, with the output driver static and i oh = 1 ma output voltage low (v ol ) 0.2 v output driver static and i ol = 1 ma
AD9531 data sheet pll1 output timing skew matrix (hstl mode ) e ntries in table 8 are typical with units of pico seconds (ps) and only apply with a channel divider input frequency less than 650 mhz. any blank cell shown in table 8 indicates an empty space in the matrix. table 8. out1_x 1 group 1a group 1b group 1c 0 1 2 3 4 5 6 7 8 9 0 20 20 20 100 100 100 100 100 100 1 20 20 100 100 100 100 100 100 2 20 100 100 100 100 100 100 3 100 100 100 100 100 100 4 20 20 20 100 100 5 20 20 100 100 6 20 100 100 7 100 100 8 20 9 1 out1_x refers to one of the 10 output chan nels associated with pll1 . pll1 output timing skew matrix (cmos mode ) e ntries in table 9 are typical with units of pico seconds (ps) and only apply with a channel divider input frequency less than 650 mhz. t he t ypical pin load is 10 pf. any blank cell shown in table 9 indicates an empty space in the matrix. table 9. out1_x 1 group 1a group 1b group 1c 0 1 2 3 4 5 6 7 8 9 0 20 20 20 100 100 100 100 100 100 1 20 20 100 100 100 100 100 100 2 20 100 100 100 100 100 100 3 100 100 100 100 100 100 4 20 20 20 100 100 5 20 20 100 100 6 20 100 100 7 100 100 8 20 9 1 out1_x refers to one of the 10 output channels associated with pll1 . pll1 output isolation, group to group table 10 . parameter min typ max unit test conditions/comments group to group isolation indicates the worst spur occurring in any channel of the noninterferer groups; all outputs of all groups are active and configured as hstl group 1a interferer 65 db group 1a = 153.6 mhz , group 1b = 122.88 mhz, group 1c = 122.88 mhz group 1b interferer 64 db group 1a = 122.88 mhz, group 1b = 153.6 mhz, group 1c = 122.88 mhz group 1c interferer 66 db group 1a = 122.88 mhz, group 1b = 122.88 mhz, group 1c = 153.6 mhz rev. 0 | page 10 of 88
data sheet AD9531 pll1 , fixed delay mode table 11. parameter min typ max unit test conditions/comments relative i nput /o utput delay external vcxo f vcxo = 122.88 mhz, f r = 15.36 mhz, f o ut = 15.36 mhz group 1a feedback from ref1_a/ ref1_ b to any group 1a output differential reference 1.60 2.45 ns 3.3 v cmos reference 0.82 1.48 ns 2.5 v cmos reference 0.64 1.37 ns group 1b feedback from ref1_a/ ref1_ b to any group 1b output differential reference 1.56 2.38 ns 3.3 v cmos reference 0.76 1.41 ns 2.5 v cmos reference 0.64 1.31 ns group 1c feedback from ref1_a/ref1_b to any group 1c output differential reference 1.79 2.60 ns 3.3 v cmos reference 0.94 1.58 ns 2.5 v cmos reference 0.84 1.41 ns internal vco f r = 122.88 mhz, f o ut = 122.88 mhz group 1a feedback from ref1_a/ref1_b to any group 1a output differential reference 1.09 2.23 ns 3.3 v cmos reference 0.36 1.64 ns 2.5 v cmos reference 0.27 1.51 ns group 1b feedback from ref1_a/ref1_b to any group 1b output differential reference 1.01 2.16 ns 3.3 v cmos reference 0.28 1.57 ns 2.5 v cmos reference 0.20 1.43 ns group 1c feedback from ref1_a/ref1_b to any group 1c output differential reference 1.14 2.32 ns 3.3 v cmos reference 0.44 1.70 ns 2.5 v cmos reference 0.37 1.56 ns pll1 internal vco table 12. parameter min typ max unit test conditions/comments internal vco frequency range 3500 3686 3900 mhz gain 53 mhz/v pll1 pfd and charge pump table 13. parameter min typ max unit test conditions/comments maximum pfd frequency 1.8 v charge pump ( internal vco) integer mode 260 mhz fractional mode 60 mhz 3.3 v charge pump (for external vcxo) 40 mhz rev. 0 | page 11 of 88
AD9531 data sheet parameter min typ max unit test conditions/comments 3.3 v charge pump current these charge pump specifications are only applic - able to the 3.3 v charge pump, which draws its power from pin 23 (vdd1_3v3) i cp sink/source programmable via register 0x 0101 , bits [d 4: d 2] highest programmable value 5.0 ma lowest programmable value 0.625 ma i cp high impedance mode leakage 0.5 na sink and source current matching 10 % 0.8 v < v cp < v dd ? 0.8 v i cp vs. v cp 11 % 0.8 v < v cp < v dd ? 0.8 v i cp vs. temperature 2 % v cp = v dd /2 pll figure of merit (fom) ? 221 dbc/hz a pplies to wide loop bandwidth mode (see the pll1 loop 2 wide bandwidth configuration section ) measured at 500 khz offset relative to the output frequency under the following conditions: f r = 245 .76 mhz (differential input), f o ut = 122.88 mhz (hstl output), integer - n pll mode, internal vco, and loop bandwidth = 500 khz pll1 rfin1 _x inputs table 14 . parameter min typ max unit test conditions/comments differential mode input frequency range 400 mhz input sensitivity 200 mv p-p capacitive coupling recommended input slew rate 100 v/s minimum limit imposed for jitter performance (when using a sinusoidal source, for example) common - mode internally generated bias voltage 0.65 v differential input resistance 5.6 k? differential input capacitance 3 pf cmos mode , single - ended input input frequency range 400 mhz input voltage high 1.2 v low 0.6 v hysteresis 300 mv input resistance 5 m? input capacitance 3 pf pll1 jitter generation the jitter integration bandwidth is from 12 khz to 20 mhz. table 15. parameter min typ max unit test conditions/comments absolute time jitter fractional mode 0.462 ps rms f r = 10 mhz, f out = 122.88 mhz, f loop = 90 khz integer mode 0.360 ps rms f r = 15.36 mhz, f out = 122.88 mhz, f loop = 100 khz wide loop bandwidth integer mode 1 0.204 ps rms f r = 122.88 mhz, f out = 122.88 mhz, f loop = 300 khz external vcxo mode 0.145 ps rms f r = 10 mhz, f out = 122.88 mhz, f loop = 100 hz additive time jitter additive jitter contribution is from the rfin1_x input to the out _ x output , excluding the vcxo contrib ution external vcxo mode 0.125 ps rms f vcxo = 122.88 mhz, f out = 122.88 mhz 1 s ee the pll1 loop 2 wide bandwidth configuration s ection. rev. 0 | page 12 of 88
data sheet AD9531 pll1 spurious performance e ntries in table 16 indicate the worst spur measured between dc and 1 ghz on any pll1 o utput for the given conditions. table 16. parameter min typ max unit test conditions/comments spurious performance rom profile 4 ? 85 dbc pll1: f r = 122.88 mhz, f loop = 300 khz; pll2: f r = 50 mhz rom profile 5 ? 85 dbc pll1: f r = 10 mhz, f vcxo = 122.88 mhz , f loop = 100 hz; pll2: f r = 50 mhz pll1 start - up time table 17. parameter min typ max unit test conditions/comments start - up time internal vco time from application of power (90% of nominal) to first output clock edge after pll1 is locked and the outputs are synchronized f r = 122.88 mhz, f out = 122.88 mhz, f pfd = 122.88 mhz, f loop = 300 khz 25 ms f r = 10 mhz, f out = 122.88 mhz, f pfd = 10 mhz, f loop = 90 khz, fractional - n pll mode 35 ms start - up time external vcxo time from application of power (90% of nominal) to first outp ut clock edge after pll1 is locked f r = 10 mhz, f out = 122.88 mhz, f pfd = 80 khz, f loop = 130 hz 840 ms pll2 characteristics pll2 reference input ( ref2_x) table 18. parameter min typ max unit test conditions/comments reference clock input path input frequency range 9.5 250 mhz input sensitivity 200 mv p -p input slew rate 100 v/s minimum limit imposed for jitter performance common - mode internally generated bias voltage 1.1 v hysteresis 95 mv differential input capacitance 3 pf differential input resistance 1 k? duty cycle 45 55 % required for input frequencies below 20 mhz when 2 frequency multiplier is in use crystal motional resistance 100 ? use a fundamental mode at - cut crystal when operating ref2_x as a crystal resonator input rev. 0 | page 13 of 88
AD9531 data sheet pll2 distribution clock outputs ( out2_0 x to out2_11 x) table 19 . parameter min typ max unit test conditions/comments hstl mode s pecifications assume a 100 ? termination across differential output pins output frequency 400 mhz rise/fall time (20% to 80%) 120 170 ps listed values are for the edge (rising or falling) with the lesser rate of change (|v/t|) duty cycle up to f out = 400 mhz 45 50 55 % differential output voltage swing 950 mv magnitude of voltage across pins; output driver static common - mode output voltage 870 mv output driver static cmos mode output frequency 150 mhz 10 pf load rise/fall time (20% to 80%) 1.0 ns 10 pf load ; listed value is for the edge (rising or falling) with the lesser rate of change (|v/t|) duty cycle 50 % 10 pf load output voltage high (v oh ) v dd ? 0.2 v relative to the vdd2_01, vdd2_24, vdd2_57, and vdd2_811 pins , with o utput driver static and i oh = 1 ma output voltage low (v ol ) 0.2 v output driver static and i ol = 1 ma pll2 output timing skew matrix (hstl mode ) e ntries in table 20 are typical with units of picoseconds (ps) and only apply with a channel divider input frequency less than 650 mhz. any blank cell shown in table 20 indicates an empty space in the matrix. table 20 . out2_x 1 group 2a group 2b group 2c group 2d 0 1 2 3 4 5 6 7 8 9 10 11 0 20 100 100 100 100 100 100 100 100 100 100 1 100 100 100 100 100 100 100 100 100 100 2 20 20 100 100 100 100 100 100 100 3 20 100 100 100 100 100 100 100 4 100 100 100 100 100 100 100 5 20 20 100 100 100 100 6 20 100 100 100 100 7 100 100 100 100 8 20 20 20 9 20 20 10 20 11 1 out2_x refers to one of the 12 output c hannels associated with pll2 . rev. 0 | page 14 of 88
data sheet AD9531 pll2 output timing skew matrix (cmos mode ) e ntries in table 21 are typical with units of pico seconds (ps) and only apply with a channel divider input frequency less than 650 mhz. t he typical pin load is 10 pf. any blank cell shown in table 21 indicates an empty space in the matrix. table 21 . out2_x 1 group 2a group 2b group 2c group 2d 0 1 2 3 4 5 6 7 8 9 10 11 0 20 100 100 100 100 100 100 100 100 100 100 1 100 100 100 100 100 100 100 100 100 100 2 20 20 100 100 100 100 100 100 100 3 20 100 100 100 100 100 100 100 4 100 100 100 100 100 100 100 5 20 20 100 100 100 100 6 20 100 100 100 100 7 100 100 100 100 8 20 20 20 9 20 20 10 20 11 1 out2_x refers to one of the 12 output c hannels associated with pll2 . pll2 output isolation, group to group table 22 . parameter min typ max unit test conditions/comments group to group isolation indicates the worst spur occurring in any channe l of the noninterferer groups; a ll outputs of all groups active and configured as hstl group 2a interferer 70 db group 2a = 125 mhz , group 2b = 156.25 mhz, group 2c = 156.25 mhz, group 2d = 156.25 mhz group 2b interferer 66 db group 2a = 156.25 mhz, group 2b = 125 mhz, group 2c = 156.25 mhz, group 2d = 156.25 mhz group 2c interferer 65 db group 2a = 156.25 mhz, group 2b = 156.25 mhz, group 2c = 125 mhz, group 2d = 156.25 mhz group 2d interferer 63 db group 2a = 156.25 mhz, group 2b = 156.25 mhz, group 2c = 156.25 mhz, group 2d = 125 mhz pll2 vco and pfd characteristics table 23 . parameter min typ max unit test conditions/comments vco frequency range 2400 2500 mhz an additional 200 ppm margin is allowed beyond these limits to accommodate input reference drift pll figure of merit (fom) ?222 dbc/hz measured at 500 khz offset from the output frequency under the following conditions: f r = 50 mhz, 3.3 v cmos (single - ended input), f o ut = 156.25 mhz, (hstl output) pfd frequency range 125 mhz rev. 0 | page 15 of 88
AD9531 data sheet pll2 jitter generation the jitter integration bandwidth is from 12 khz to 20 mhz . table 24. parameter min typ max unit test conditions/comments jitter generation f r = 25 mhz, f out = 156.25 mhz 0.566 ps rms f r = 50 mhz, f out = 156.25 mhz 0.337 ps rms pll2 spurious performance e ntries in table 25 indicate the worst spur measured between dc and 1 ghz on any pll2 o utput for the given conditions. table 25. parameter min typ max unit test conditions/co mments spurious performance rom profile 4 pll1: f r = 122.88 mhz, f loop = 300 khz; pll2: f r = 50 mhz out2_0 to out2_4 ? 61 dbc out2_5 to out2_7 ? 69 dbc out2_8 to out2_11 ? 78 dbc rom profile 5 pll1: f r = 10 mhz, f vcxo = 122.88 mhz , f loop = 100 hz; pll2: f r = 50 mhz; pll3: f r = 10 mhz, c load = 10 pf on out3_1p out2_0 ? 76 dbc out2_1 ? 65 dbc out2_2 to out2_3 ? 69 dbc out2_4 to out2_11 ? 79 dbc pll2 start - up time table 26. parameter min typ max unit test conditions/comments start - up time the time from the application of power (90% of nominal) to the first output clock edge (pll2 is locked and outputs are synchronized) f r = 25 mhz, f out = 156.25 mhz, f pfd = 25 mhz 50 ms rev. 0 | page 16 of 88
data sheet AD9531 pll3 characteristics pll3 reference input (ref3 _x ) table 27. parameter min typ max unit test conditions/comments reference input path input frequency range 9.5 100 mhz input sensitivity 200 mv p -p minimum input slew rate 100 v/s minimum limit imposed for jitter performance common - mode , internally generated bias voltage 1.16 v hysteresis 70 mv differential input capacitance 3 pf differential input resistance 4.1 k? duty cycle 47 53 % required for input frequencies below 20 mhz when using a frequency scale factor of either 2 or 2/3 crystal motional resistance 100 ? use a fundamental mode at - cut crystal when operating ref3_x as a crystal resonator input pll3 outputs out3_0 table 28. parameter min typ max unit test conditions/comments 1.8 v supply (cmos) output frequency 150 mhz 10 pf load rise/fall time (20% to 80%) 1.0 ns 10 pf load ; listed value is for the edge (rising or falling) with the lesser rate of change (|v/t|) duty cycle 50 % 10 pf load output voltage high (v oh ) v dd ? 0.2 v relative to vdd 3_01 (p in 66 ) with output driver static and i oh = 1 ma output voltage low (v ol ) 0.2 v output driver static and i ol = 1 ma 3.3 v supply (cmos) output frequency 200 mhz 10 pf load rise/fall time (20% to 80%) 0.7 ns 10 pf load ; listed value is for the edge (rising or falling) with the lesser rate of change (|v/t|) duty cycle 50 % 10 pf load output voltage high (v oh ) v dd ? 0.2 v relative to vdd 3_3v3 (p in 67 ) with output driver static and i oh = 1 ma output voltage low (v ol ) 0.2 v output driver static and i ol = 1 ma pll3 outputs ( out3_1 x) table 29. parameter min typ max unit test conditions/comments hstl mode output frequency 400 mhz rise/fall time (20% to 80%) 120 170 ps 100 ? termination across the output pins ; listed values are for the edge (rising or falling) with the lesser rate of change (|v/t|) duty cycle 45 50 55 % differential output voltage swing 925 mv magnitude of voltage across the pins; output driver static common - mode output voltage 850 mv output driver static rev. 0 | page 17 of 88
AD9531 data sheet parameter min typ max unit test conditions/comments lvds mode output frequency 400 mhz rise/fall time (20% to 80%) 160 ps 100 ? termination across the output pair ; listed value is for the edge (rising or falling) with the lesser rate of change (|v/t|) duty cycle 45 50 55 % differential output voltage swing balanced, v od 247 454 mv voltage swing between the output pins; output driver static unbalanced, v od 50 mv absolute difference between the voltage swing of the out3_xp pin and the out3_xn pin; output driver static offset voltage common - mode, v os 1.125 1.26 1.375 v output driver static common - mode difference, v os 50 mv voltage difference between the out3_xp pin and the out3_xn pin ; output driver static short - circuit output current 13 24 ma output driver static cmos mode 1.8 v supply output frequency 150 mhz 10 pf load rise/fall time (20% to 80%) 1.0 ns 10 pf load ; listed value is for the edge (rising or falling) with the lesser rate of change (|v/t|) duty cycle 50 % 10 pf load output voltage high (v oh ) v dd ? 0.2 v relative to vdd 3_01 (p in 66 ) with output driver static and i oh = 1 ma output voltage low (v ol ) 0.2 v output driver static and i ol = 1 ma 3.3 v supply output frequency 200 mhz 10 pf load rise/fall time (20% to 80%) 0.7 ns 10 pf load ; listed value is for the edge (rising or falling) with the lesser rate of change (|v/t|) duty cycle 50 % 10 pf load output voltage high (v oh ) v dd ? 0.2 v relative to vdd 3_3v3 (p in 67 ) with output driver static and i oh = 1 ma output voltage low (v ol ) 0.2 v output driver static and i ol = 1 ma pll3 vco and pfd characteristics the specifications in table 30 apply to both the input and output plls of pll3. table 30. parameter min typ max unit test conditions/comments vco frequency range 720 805 mhz an additional 200 ppm margin is allowed beyond these limits to accommodate input reference drift pll figure of merit (fom) ?215 dbc/hz measured at 100 khz offset from the output frequency under the following condition s: f r = 10 mhz (3.3 v cmos single - ended input), f o ut = 125 mhz (hstl output) pfd frequency range 9.5 100 mhz rev. 0 | page 18 of 88
data sheet AD9531 pll3 spurious performance e ntries in table 31 indicate the worst spur measured between dc and 600 mhz on ou t3_1p for the given conditions. table 31. parameter min typ max unit test conditions/comments spurious performance rom profile 4 pll1: f r = 122.88 mhz, f loop = 300 khz; pll2: f r = 50 mhz out2_0 to out2_4 ? 61 dbc out2_5 to out2_7 ? 69 dbc out2_8 to out2_11 ? 78 dbc rom profile 5 pll1: f r = 10 mhz, f vcxo = 122.88 mhz , f loop = 100 hz; pll2: f r = 50 mhz; pll3: f r = 10 mhz, c load = 10 pf on out3_1p out2_0 ? 76 dbc out2_1 ? 65 dbc out2_2 to out2_3 ? 69 dbc out2_4 to out2_11 ? 79 dbc pll3 jitter generation u nless otherwise specifi ed the following test conditions apply : pll1 configured with out1_0 to out1_9 operating at 122.88 mhz in hstl mode; pll2 configured with f ref = 50 mhz , f vco = 2.5 ghz, and out2_0 to out2_11 operating at 125 mhz in hstl mode; pll3 configured for single loop o peration with out3_0 disabled. measurements are valid with the pll2 input reference locked to an integer multiple of the pll3 input reference frequenc y to within 4.8 ppm. table 32. parameter min typ max unit test conditions/comments jitter generation f r = 25 mhz; f out = 100 mhz out1_8 x and out1_ 9 x disabled 1.78 ps rms out1_8x and out1_9x active 3.17 ps rms f r = 10 mhz; f out = 125 mhz pll1 and pll2 powered down 2.69 ps rms out1_8x and out1_9x disabled 2.95 ps rms out1_8x and out1_9x active 5.20 ps rms pll3 start - up time the ppl3 start - up t ime is the time from the application of power (90% of nominal) to the first output clock edge (pll3 is locked and the outputs are synchronized). table 33. parameter min typ max unit test conditions/comments start - up time f r = 10 mhz, f out = 25 mhz, f pfd = 10 mhz 20 ms rev. 0 | page 19 of 88
AD9531 data sheet serial control port table 34. parameter min typ max unit test conditions/comments input (scl k, sdio, cs ) 1.8 v supply dvdd_io (pin 18) powered with 1.8 v input voltage logic 1 1.3 v logic 0 0.6 v input current (i inh , i inl ) ? 2 + 2 a input capacitance 3 pf 3.3 v supply dvdd_io (p in 18) powered with 3.3 v input voltage logic 1 1.3 v logic 0 0.6 v input current (i inh , i inl ) ? 2 + 2 a input capacitance 3 pf output (sdio) 1.8 v supply dvdd_io (pin 18) powered with 1.8 v output voltage logic 1 v dd ? 0.2 v 1 ma load current logic 0 0.2 v 1 ma load current 3.3 v supply dvdd_io (pin 18) powered with 3.3 v output voltage logic 1 v dd ? 0.2 v 1 ma load current logic 0 0.2 v 1 ma load current serial control port timing table 35. parameter min typ max unit test conditions/comments 1.8 v supply dvdd_io ( pin 18) powered with 1.8 v sclk clock rate, 1/t sc lk 50 mhz pulse width high, t high 2.1 ns pulse width low, t low 1.7 ns sdio to sclk setup, t ds 0.3 ns sclk to sdio hold, t dh 1.0 ns sclk to valid sdio, t dv 6.5 ns cs to sclk setup (t s ) and hold (t h ) 1.1 ns cs minimum pulse width high 1.4 ns 3.3 v supply dvdd_io ( pin 18) powered with 3.3 v sclk clock rate, 1/t sc lk 50 mhz pulse width high, t high 0.8 ns pulse width low, t low 2.5 ns sdio to sclk setup, t ds 1.8 ns sclk to sdio hold, t dh 0.4 ns sclk to valid sdio, t dv 6.5 ns cs to sclk setup (t s ) and hold (t h ) 2.4 ns cs minimum pulse width high 3.0 ns rev. 0 | page 20 of 88
data sheet AD9531 absolute maximum rat ings table 36. parameter rating analog supply voltage 3.3 v supply pins 3.6 v 1.8 v supply pins 2 v maximum digital input voltage ?0.5 v to vdd3 + 0.5 v storage temperature range ?65c to +150c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in t he operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution rev. 0 | page 21 of 88
AD9531 data sheet pin configuration an d function descriptions 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 29 30 31 32 33 34 36 37 35 38 39 40 41 58 57 56 55 54 53 52 51 50 49 48 47 46 45 59 60 61 62 63 64 65 66 78 77 76 75 74 73 72 71 70 69 68 67 79 80 81 82 83 84 85 86 87 88 21 22 42 43 44 AD9531 t o p view (not to scale) out2_4n vdd1_3v3 lor/m4 vdd3_01 notes 1. the exposed p ad on the bot t om of the p ackage must be soldered t o ground t o achieve the specified therma l performance. out2_4 p vdd2_24 out2_3n out2_3 p out2_2n out2_2 p ldet2/m2 out2_1n out2_1 p vdd2_01 out2_0n out2_0 p vdd2 ref2_n ref2_ p vdd2 ldoreg2 vdd2_3v3 out3_1n out3_1 p vdd3_3v3 out3_0 vdd3 ref3_n ref3_ p vdd3 ldet3/m3 out1_9n out1_9 p vdd1_89 out1_8n out1_8 p ldet1/m1 out1_7n out1_7 p out1_6n out1_6 p vdd1_47 out1_5n out1_5 p out1_4n out1_4 p out2_5 p out2_5n out2_6 p out2_6n vdd2_57 out2_7 p out2_7n out2_8 p out2_8n out2_9 p out2_9n vdd2_8 1 1 out2_10 p out2_10n out2_ 1 1 p out2_ 1 1n dvdd_io cs dvdd sclk sdio ref1_a p ref1_an ref1_se l ref1_b p ref1_ bn vdd1 vdd1_3v3 ldoreg1 rfin1_ p lf rfin1_n vdd1 out1_0 p out1_0n out1_1 p out1_1n vdd1_03 out1_2 p out1_2n out1_3 p out1_3n 12973-002 figure 2 . pin configuration table 37 . pin function descriptions pin no. mnemonic supply domain description 1 lor/m4 1.8 v/3.3 v loss of reference pin. this is a multifunction pin. 2 out2_5p 1.8 v pll2 output 5 ( positive ) . 3 out2_5n 1.8 v pll2 output 5 ( negative ) . 4 out2_6p 1.8 v pll2 output 6 ( positive ) . 5 out2_6n 1.8 v pll2 output 6 ( negative ) . 6 vdd2_57 1.8 v pll2 power supply for channel outputs out2_5 through out2_7 . 7 out2_7p 1.8 v pll2 output 7 ( positive ) . 8 out2_7n 1.8 v pll2 output 7 ( negative ) . 9 out2_8p 1.8 v pll2 output 8 ( positive ) . 10 out2_8n 1.8 v pll2 output 8 ( negative ) . 11 out2_9p 1.8 v pll2 output 9 ( positive ) . 12 out2_9n 1.8 v pll2 output 9 ( negative ) . 13 vdd2_811 1.8 v pll2 power supply for channel outputs out2_8 through out2_11 . 14 out2_10p 1.8 v pll2 output 10 ( positive ) . 15 out2_10n 1.8 v pll2 output 10 ( negative ) . 16 out2_11p 1.8 v pll2 output 11 ( positive ) . 17 out2_11n 1.8 v pll2 output 11 ( negative ) . 18 dvdd_io 1.8 v/3.3 v power supply for serial i nput /o utput pins. 19 cs 1.8 v/3.3 v chip select pin. 20 dvdd 1.8 v power supply for spi registers and pll1 digital - modulator (sdm). 21 sclk 1.8 v/3.3 v serial programming clock. 22 sdio 1.8 v/3.3 v serial data input/output. 23 vdd1_3v3 3.3 v pll1 ref _ a/ ref _ b input receiver power supply. 24 ref1_ap 3.3 v pll1 ref _ a input ( positive ). use this pin when operating the ref _ a input in single - ended mode. rev. 0 | page 22 of 88
data sheet AD9531 pin no. mnemonic supply domain description 25 ref1_an 3.3 v pll1 ref _ a input (negative). when operating the ref _ a input in single - ended mode, this pin becomes inoperative (internally disconnected) and must be connected to ground or left floating. 26 ref1_sel 3.3 v pll1 manual ref _ a/ref _ b input select. 27 ref1_bp 3.3 v p ll1 ref _ b input (positive). use this pin when operating the ref _ b input in single - ended mode. 28 ref1_bn 3.3 v pll1 ref _ b input (negative). when operating the ref _ b input in single - ended mode, this pin becomes inoperative (internally discon nected) and must be connected to ground or left floating. 29 vdd1 1.8 v pll1 power supply for the input circuitry following the ref1_a/ ref1_ b receivers. 30 vdd1_3v3 3.3 v pll1 power supply for the low dropout ( ldo ) input. 31 ldoreg1 3.3 v pll1 ldo regulated supply for the vco core. connect a 220 nf capacitor between this pin and ground. 32 lf 3.3 v loop filter. 33 rfin1_p 3.3 v pll1 external vco/vcxo input (positive). 34 rfin1_n 3.3 v pll1 external vco/vcxo input (negative). 35 vdd1 1.8 v pll1 power supply for the output distribution circuitry. 36 out1_0p 1.8 v pll1 output 0 (positive). 37 out1_0n 1.8 v pll1 output 0 (negative). 38 out1_1p 1.8 v pll1 output 1 (positive). 39 out1_1n 1.8 v pll1 output 1 (negative). 40 vdd1_03 1.8 v pll1 power supply for channel outputs out1_0 through out1_3. 41 out1_2p 1.8 v pll1 output 2 (positive). 42 out1_2n 1.8 v pll1 output 2 (negative). 43 out1_3p 1.8 v pll1 output 3 (positive). 44 out1_3n 1.8 v pll1 output 3 (negative). 45 out1_4p 1.8 v pll1 output 4 (positive). 46 out1_4n 1.8 v pll1 output 4 (negative). 47 out1_5p 1.8 v pll1 output 5 (positive). 48 out1_5n 1.8 v pll1 output 5 (negative). 49 vdd1_47 1.8 v pll1 power supply for channel outputs out1_4 through out1_7. 50 out1_6p 1.8 v pll1 output 6 (positive). 51 out1_6n 1.8 v pll1 output 6 (negative). 52 out1_7p 1.8 v pll1 output 7 (positive). 53 out1_7n 1.8 v pll1 output 7 (negative). 54 ldet1/m1 1.8 v/3.3 v pll1 lock detect. this is a multifunction pin. 55 out1_8p 1.8 v pll1 output 8 (positive). 56 out1_8n 1.8 v pll1 output 8 (negative). 57 vdd1_89 1.8 v pll1 power supply for channel outputs out1_8 through out1_9. 58 out1_9p 1.8 v pll1 output 9 (positive). 59 out1_9n 1.8 v pll1 output 9 (negative). 60 ldet3/m3 1.8 v/3.3 v pll3 lock detect. this is a multifunction pin. 61 vdd3 1.8 v pll3 power supply for input circuitry of the first pll in the 2 pll cascade of pll3. 62 ref3_p 1.8 v pll3 reference input (positive). 63 ref3_n 1.8 v pll3 reference input (negative). 64 vdd3 1.8 v pll3 power supply for the output circuitry of pll3a and input circuitry of pll3b . 65 out3_0 1.8 v/3.3 v pll3 output 0 . 66 vdd3_01 1.8 v pll3 power supply for channel outputs out3_0 through out3_1 . 67 vdd3_3v3 3.3 v pll3 power supply for the output circuitry. 68 out3_1p 1.8 v/3.3 v pll3 output 1 ( positive ) . 69 out3_1n 1.8 v/3.3 v pll3 output 1 ( negative ) . 70 vdd2_3v3 3.3 v pll2 power supply for the ldo input. 71 ldoreg2 1.8 v pll2 l do regulated supply for the vco core. connect a 220 nf capacitor between this pin and ground. rev. 0 | page 23 of 88
AD9531 data sheet pin no. mnemonic supply domain description 72 vdd2 1.8 v pll2 power supply for the input circuitry. 73 ref2_p 1.8 v pll2 reference input (positive). 74 ref2_n 1.8 v pll2 reference input (negative). 75 vdd2 1.8 v pll2 power supply for the output circuitry. 76 out2_0p 1.8 v pll2 output 0 (positive). 77 out2_0n 1.8 v pll2 output 0 (negative). 78 vdd2_01 1.8 v pll2 power supply for outputs out2_0 through out2_1. 79 out2_1p 1.8 v pll2 output 1 (positive). 80 out2_1n 1.8 v pll2 output 1 (negative). 81 ldet2/m2 1.8 v/3.3 v pll2 lock detect. this is a multifunction pin. 82 out2_2p 1.8 v pll2 output 2 (positive). 83 out2_2n 1.8 v pll2 output 2 (negative). 84 out2_3p 1.8 v pll2 output 3 (positive). 85 out2_3n 1.8 v pll2 output 3 (negative). 86 vdd2_24 1.8 v pll2 power supply for outputs out2_2 through out2_4. 87 out2_4p 1.8 v pll2 output 4 (positive). 88 out2_4n 1.8 v pll2 output 4 ( negative ) . ep exposed pad . the exposed pad on the bottom of the package must be soldered to ground to achieve the specified thermal performance. rev. 0 | page 24 of 88
data sheet AD9531 typical performance characteristics nominal supply voltage for v dd = 3.3 v and 1.8 v, unless otherwise noted . j itter integration bandwid th = 12 khz to 20 mhz. in the typical performance characteristics section, the following terminology is used: f r is the device input reference clock frequency, f out is the device output clock frequency, lbw is the loop bandwidth of pll x, and lbw 2 is the loop bandwidth of pll x with the 2 multiplier enabled . pll1 characteristics frequenc y offset (hz) C160 C155 C150 C145 C140 C135 C130 C125 C120 C 1 15 C 1 10 C105 C100 C165 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) 12973-003 jitter: 461fs rms jitter b w : 12khz t o 20mhz figure 3. absolute phase noise, f r = 10 mhz, f out = 122.88 mhz, 3.3 v cmos s ingle - e nded input , hstl output , frac tional - n pll mode , int ernal vco , lbw = 100 khz frequenc y offset (hz) C160 C155 C150 C145 C140 C135 C130 C125 C120 C1 15 C1 10 C105 C100 C95 100 1k 10k 100k 1m 10m 100m jitter: 145fs rms jitter b w : 12khz t o 20mhz vcxo specific a tion manu f acturer: t aitien p/n: vteualjanf-122.88000 phase noise (dbc/hz) 12973-004 4 10 12288 33 - - 100 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequenc y offset (hz) C165 C160 C155 C150 C145 C140 C135 C130 C125 C120 C 1 15 C 1 10 jitter b w : 12khz t o 20mhz f r = 122.88mhz jitter: 205fs rms f r = 245.76mhz jitter: 169fs rms 12973-005 5 12288 24576 12288 - 300 2 565 rev. 0 | page 25 of 88
AD9531 data sheet pll2 characteristics frequenc y offset (hz) 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) C165 C160 C155 C150 C145 C140 C135 C130 C125 C120 C 1 15 C 1 10 jitter b w : 12khz t o 20mhz f r = 25mhz jitter: 564fs rms f r = 50mhz jitter: 333fs rms 12973-006 figure 6 . absolute phase noise, f r = 25 mhz and 50 mhz, f out = 156.25 mhz, 3.3 v cmos single - ended input , hstl output frequenc y offset (hz) 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) C165 C160 C155 C150 C145 C140 C135 C130 C125 C120 C 1 15 C 1 10 jitter b w : 12khz t o 20mhz f r = 25mhz jitter: 569fs rms f r = 50mhz jitter: 338fs rms 12973-007 7 25 50 125 33 - rev. 0 | page 26 of 88
data sheet AD9531 pll3 characteristics frequenc y offset (hz) 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) C160 C155 C150 C145 C140 C135 C130 C125 C120 C 1 15 C100 C 1 10 C105 jitter: 2.74ps rms jitter b w : 12khz t o 20mhz 12973-008 figure 8 . absolute phase noise, f r = 10 mhz, f out = 125 mhz, 3.3 v cmos single - ended input , hstl output frequenc y offset (hz) 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) C160 C155 C150 C145 C140 C135 C130 C125 C120 C 1 15 C100 C 1 10 C105 jitter: 1.5ps rms jitter b w : 12khz t o 20mhz 12973-009 9 25 133 33 - frequenc y offset (hz) 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) C160 C155 C150 C145 C140 C135 C130 C125 C120 C1 15 C100 C1 10 C105 jitter: 4.47ps rms jitter b w : 12khz t o 20mhz 12973-010 10 192 125 33 - rev. 0 | page 27 of 88
AD9531 data sheet general characterist ics frequenc y (mhz) 0 1 2 3 4 25 75 50 100 150 175 200 125 225 peak- t o-peak vo lt age (v) 3.3v cmos 1.8v cmos 12973-0 1 1 figure 11 . cmos output amplitude (peak - to - peak voltage) vs. frequency rev. 0 | page 28 of 88
data sheet AD9531 terminology phase jitter and phase noise an ideal sine wave has a continuous and even progression of phase with time from 0 to 360 for each cycle. a sine wave as a real - world signal, however, exhibits a certain amount of variation in its phase progression over time relative to the ideal sine wave. this variation is phase jitter. although many causes can contribute to phase jitter, one major cause is random noise, characterized statistically by a normal (gaussian) distribution . in the frequency domain, an ideal sine wave exhibits a discrete sp ectral line. phase jitter, however, blurs the ideal spectral line because it distributes some of the energy of the sine wave throughout the frequency spectrum , resulting in a continuous, rather than discrete, power spectrum. this power spectrum usually app ears in the literature as a table of values given in units of dbc/hz at various offset frequencies from the frequency of the sine wave (carrier). the units, dbc/hz, represent a ratio (expressed in decibels) of the power contained within a 1 hz bandwidth at some specified offset frequency from the carrier and relative to the power in the carrier. in fact, the c in dbc is an abbrev - ia tion for carrier and signifies d ecibels relative to the carrier . it is important to integrate the total power contained within some interval of offset frequencies (for example, 10 khz to 10 mhz). this is integrated phase noise and relates phase noise (a frequency domain parameter) over the given bandwidth to jitter (a time domain parameter). phase noise has a detrimental effect o n the performance of analog - to - digital converters ( adcs ) , digital - to - analog converters ( dacs ) , and radio frequency ( rf ) mixers. phase noise lowers the achievable dynamic range of the converters and mixers, although it affects the se various devices in diffe rent ways. time jitter phase noise is a frequency domain phenomenon. in the time domain, the same effect appears as time jitter, which is a variation of the instants of zero crossing of a sine wave (or a variation in the occurrence of the edges of a squar e wave relative to their ideal position in time). in both cases, timing jitter is variations relative to the ideal timing instants. because time jitter variations are random in nature, they carry units of seconds root mean square (rms), which corresponds t o the standard deviation () of a normal (gaussian) distribution. time jitter that occurs on a sampling clock for a dac or an adc decreases the signal - to - noise ratio (snr) and dynamic range of the converter. a sampling clock with the lowest possible jitter allows the highest possible performance from a given converter. additive phase noise additive phase noise is the amount of phase noise attributable to the device or subsystem in question. that is, additive phase noise is phase noise exhibited only by the device in question and effectively disregards the phase noise contributions of other sources (like external oscillators or clock sources). this disregarded phase noise makes it po ssible to predict the impact of the device in question on the total system ph ase noise when used in conjunction wit h the various oscillators and clock sources (each contributing its own phase noise to the total). in many cases, the phase noise of one element dominates the system phase noise. when there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. additive time jitter additive time jitter is the sa me as additive phase noise, except it is applicable to the time domain rather than the frequency domain . rev. 0 | page 29 of 88
AD9531 data sheet theory of operation the AD9531 includes three inde pendent, fully integrated plls that enable three separate frequency translations (pll1, pll2 , and pll3 in figure 1 ). the device has a serial programming interface (spi) that allows fu ll contro l of its many features, as well as multifunction pins enabling the device to power up in one of 16 possible predefined configurations. because pll1, pll2 , and pll3 are functionally independent, their descriptions appear in the following three distinct sect ions: ? the pll1 integer/fractional - n pll section ? the pll1 lock detector section ? the pll3 integer - n pll section pll1 integer/fractional - n pll pll1 is a fractional - n pll that is also capable of operating in integer mode (see figure 12). pll1 provides two independent reference clock input signals. the AD9531 supports differential and single - ended operation for both reference clocks. pll1 provides 10 outputs segregated into three groups. each group has a dedicated channel divider , allowing the device to produce three different output frequencies simultaneously. note that pll1 is capable of severa l different loop conf igurations; this data sheet describes each configuration separately. pll1 vco pfd switch over contro l sdm ref1_ax dld holdover contro l tris ta te charge pum p 1.8v charge pum p 3.3v charge pum p loo p 1 loo p 2 vdd1_3v3 ldoreg1 ldet1/m1 interna l loo p fi l ter lf rfin_x t o charge pumps out1_0x n1 a n1b m1 d1 a d1c d1b 2 loo p fi l ter component (interna l vco) loo p fi l ter components + externa l vcxo vcxo 3.3v vcxo l vcmos (single-ended) or l vpec l (differential) output rz r3 c3 cp ref1_bx ref1_se l out1_1x out1_2x out1_3x out1_4x out1_5x out1_6x out1_7x out1_8x out1_9x r1 loo p 3 loo p 4 3.5ghz t o 3.9ghz 12973-013 figure 12 . pll1 block diagram rev. 0 | page 30 of 88
data sheet AD9531 pll1 loop configurat ions the s election of the various pll1 loop configurations depends on the following three criteria: ? the fixed delay bits (register 0x 0101 , bits [ d 6: d 5]) . ? the external oscillator (vxco) mode bits (register 0x 0101 , bits [ d 1: d 0]) . ? the n1b divider value . a summary of the criteria necessary to select the various loop configurations is shown in table 38. table 38. pll1 loop configurations 1 register 0x 0101 n1b loop vco bits [ d 6: d 5] bits [ d 1: d 0] 0 0 0 or 1 1 internal 0 0 > 1 2 internal 0 > 0 x 3 external > 0 0 x 4 internal > 0 > 0 x 4 external 1 x means dont care. pll1 loop 1 configuration (integrated vco) in the loop 1 configuration, the loop bandwidth of pll1 is constant at a nominal value of 100 khz. the pfd of the pll drives a 1.8 v charge pump, which automatically changes its output current proportional to the value of n1a , thereby keeping the loop bandwidth constant regardless of the frequency translation ratio. the vco frequency is a function of the pfd input frequency (see the pll1 reference frequency scaling section ) and the values programmed into the registers associated with n1a, n1a fraction, and n1a modulus . ? ? ? ? ? ? ? ? + = modulus n1a fraction n1a n1a f f pfd vco r f vco is the frequency of the vco . f pfd is the frequency at the input to the pfd . n1a is an element of the following set: {n min , n min + 1, ... 255}, where n min = 15 for integer - n operation and n min = 80 for fractional - n operation. n1a fraction is an element of the following set: {0, 1 ... 1,048,574}. n1a modulus is an element of the following set, but with the constraint of n1a fraction < n1a modulus : {1, 2 ... 1,048,575}. out1_x and is an element of the following set: {1, 2 ... 256}. note that programming n1a f raction to 0 disables the sdm and configures pll1 as an integer - n pll. integer - n operation yields the best performance in terms of phase noise, spurs, and jitter. the overall frequency translation equation for loop 1 is as follows : d1 m1 modulus n1a fraction n1a n1a r1 f f ref out1 ? ? ? ? ? ? ? ? + = f out 1 is the frequency at out1_x. f ref is the frequency of the acti ve reference (ref_1a or ref_1b). r1 is an element of the following set: {?, 1, 4, 5 ... 4,095}. the value of ? is the result of selecting the 2 reference multiplier (by programming the r1 divider to a value of 0). m1 is an element of the following set: {3, 4 ... 11}. d1 is the channel divider (d1a, d1b, or d1c) associated with loo p fi l ter vco sdm n1 a m1 distribution ref1_ax ref1_bx out1_0x out1_9x ref1_se l rfin1_x AD9531: pll1 pfd 1.8v c p reference input lf ldoreg1 12973-014 13 1 1 rev. 0 | page 31 of 88
AD9531 data sheet loo p fi l ter vco n1b n1 a m1 distribution ref1_ax ref1_bx out1_0x out1_9x ref1_se l rfin1_x AD9531: pll1 pfd 1.8v cp reference input lf ldoreg1 12973-015 figure 14 . pll1 loop 2 configuration loo p fi l ter vco n1 a m1 distribution ref1_ax ref1_bx out1_0x out1_9x ref1_se l rfin1_x AD9531: pll1 pfd 1.8v cp reference input lf ldoreg1 12973-016 15 1 2 pll1 loop 2 configuration (integrated vco) loop 2 consists of the n1a and n1b divid ers in cascade , allowing lower pfd frequencies than in the loop 1 configuration . in this configuration, t he charge pump current is constant at 1200 a ( there is no automatic scaling as in the loop 1 configuration). furthermo re, an internal switch shorts rz in the integrated loop filter and automatically sets t he integrated pole capacitor (c p ) to 50 pf. this particular internal loop filter configuration provides the flexibility to set the response zero and first pole frequency of the loop filter (via an exte rnal r c network) to accommodate a low pfd rate. note that loop 2 configures pll1 as an integer - n pll only. the vco frequency is a function of the pfd input frequency (see the pll1 reference frequency scaling section ) and the values programmed into the registers associated with n1a and n1b. f vco = f pfd n1a n1b where: n1a is an element of the following set: {15, 16 ... 255}. n1b is an element of the following set: {4, 5 ... 4095}. the overall frequency translation equation for loop 2 is as follows : d1 m1 n1b n1a r1 f f ref out1 = f out1 is the frequency at out1_x. f ref is the frequency of the acti ve reference (ref_1a or ref_1b) . r1 is an element of the following set: {?, 1, 4, 5 ... 4,095}. the value of ? is the result of selecting the 2 reference multiplier (by programming the r1 divider to a value of 0). out1_x and is also an element of the following set: {1, 2 ... 256}. pll1 loop 2 wide bandwidth configuration to select the loop 2 wide bandwidth configuration configure the device for loop 1 operation per table 38 , but set the wide bandwidth mode bit (register 0x0102, bit d 3) to logic 1. the loop 2 wide bandwidth configuration is for applications requiring improved jitter performance. it is identical to the standard loop 2 configuration in most respects. however, there are t wo significant differences. first, n1b is not part of the feedback path. second, although not shown in figure 15 , the sdm drives the n1a divider as in the loop 1 configuration. in the loop 2 wide bandwidth configuration however, the sdm tends to degrade jitter performance significantly. therefore, when using the loop 2 wide bandwidth configuration , it is bes t to operate in integer - n mode, which accounts for the exclusion of the sdm from figure 15. the vco frequency is a function of the pfd input frequency (see the pll1 reference frequency scaling section ) and the value programmed into the register associated with n1a. f vco = f pfd n1a where n1a is an element of the following set: {15, 16 ... 255}. the overall frequency translation equation for loop 2 wide bandwidth is as follows : d1 m1 n1a r1 f f ref out1 = f out1 is the frequency at out1_x. f ref is the frequency of the acti ve reference (ref_1a or ref_1b ) . r1 is an element of the following set: {?, 1, 4, 5 . .. 4,095}. the value of ? is the result of selecting the 2 reference multiplier (by programming the r1 divider to a value of 0). m1 is an element of the following set: {3, 4 ... 11}. d1 is t he channel divider (d1a, d1b, or d1c) associated with out1_x and is also an element of the following set: {1, 2 ... 256}. rev. 0 | page 32 of 88
data sheet AD9531 loo p fi l ter 3.3v c p vco n1b distribution ref1_ax ref1_bx out1_0x out1_9x ref1_se l rfin1x AD9531: pll1 pfd reference input lf ldo reg 1 12973-017 figure 16 . pll1 loop 3 configuration loo p fi l ter vco m1 distribution ref1_ax ref1_bx out1_0x out1_9x ref1_se l rfin1x AD9531: pll1 pfd 1.8v cp reference input lf ldo reg 1 12973-018 17 1 4 pll1 loop 3 configuration (external vcxo) the loop 3 configuration enables the rfin receiver and the 3.3 v charge pump. note that an external loop filter is required between the lf pin and the control input of the external vcxo. the vcxo frequency is a function of the pfd input frequency (see the pll1 reference frequency scaling section ) and the value programmed into the register associated n1b. f vcxo = f pfd n1b where n1b is an element of the following set: {1, 4, 5 ... 4,095}. the overall frequency translation equation for loop 3 is as follows : d1 n1b r1 f f ref out = 1 where: f out 1 is the frequency at out1_x. f ref is the frequency of the activ e reference (ref_1a or ref_1b ). r1 is an element of the following set : {?, 1, 4, 5 ... 4,095}. the value of ? is the result of selecting the 2 reference multiplier (by programming the r1 divider to a value of 0). d1 is the channel divider (d1a, d1b, or d1c) associated with out1_x and i s also an element of the following set: {1, 2 ... 256}. pll1 loop 4 configuration (integrate d vco or external vcxo) the loop 4 configuration has two variants: internal and external. the internal configuration uses the internal vco, whereas the external configuration relies on an external vcxo. note that the loop 4 configuration bypasses the n1b d ivider, which the block diagram of pll1 ( see figure 12 ) does not explicitly show. the loop 4 configuration provides a fixed delay function, which results from the channel dividers being synchronized to each other and the input to the pfd originat ing from one of the output drivers ( per register 0x 0101 , bits [ d 6: d 5]) . that is, the feedback reference point of the pll is one of the outputs, which yields the fixed delay function. the fixed delay function effectively edge aligns all the outputs (out1_x) with the reference input because , by design, the internal delay of the reference path closely matches the internal feedback delay from the chann el dividers. internal loop 4 configuration in the internal loop 4 configuration, the feedback divider consists o f m1 and one of the channel dividers (d1a, d1b , or d1c) in cascade. the particular channel divider included in the feedback path depends on the fixed delay bits per table 57. f vco = f pfd ( m1 d1 ) where: m1 is an element of the following set: {3, 4 ... 11}. d1 is the channel divider (d1a, d1b, or d1c) associated with out1_x. d1 is also an element of the following set: {1, 2 ... 256}. the overall frequency translation equation for loop 4 using the internal vco is as follows : d1 m1 r1 f f ref out1 = f out1 is the frequency at out1_x. f ref is the frequency of the active reference (ref_1a x or ref_1b x). r1 is an element of the following set: {?, 1 , 4, 5 ... 4,095}. the value of ? is the result of selecting the 2 reference multiplier (by programming the r1 divider to a value of 0). note that internal loop 4 configuration still allows calibration of the internal vco, but requires special treatment ( see the pll1 internal vco calibration section). rev. 0 | page 33 of 88
AD9531 data sheet loo p fi l ter 3.3v cp vcxo distribution ref1_ax ref1_bx out1_0x out1_9x ref1_se l rfin1x AD9531: pll1 pfd reference input lf ldo reg 1 12973-019 figure 18 . pll1 external loop 4 configuration external loop 4 configuration in the external loop 4 configuration, the feedback divider consists of one of the channel dividers (d1a, d1b , or d1c). the particular channel divider included in the feedback path, d1x, depends on t he fixed delay bits (register 0x 0101 , bits [ d 6: d 5]) . note that m1 is not part of the feedback path in this configuration . the external configuration uses the 3.3 v charge pump and an external loop filter and vcxo. f vcxo = f pfd d1 where d1 is the channel divider (d1a, d1b, or d1c) associated with out1_x. d1 is also an element of the following set: {1, 2 ... 256}. the overall frequency translation equation for loop 4 using an external vcxo is as follows : d1 r1 f f ref out1 = f out1 is the frequency at out1_x. f ref is the frequency of the active reference (ref_1a x or ref_1b x). r1 is an element of the following set: {?, 1, 4, 5 ... 4,095}. t he value of ? is the result of selecting the 2 reference multiplier (by programming the r1 divi der to a value of 0). pll1 reference clock inputs (ref1_a x / ref1_ b x ) two pairs of pins, ref1_a x and ref1_b x, provide access to the reference clock receivers. to accommodate input signals with slow rising and falling edges, both the differential and single - ended in put receivers use hysteresis. hysteresis also ensures that a disconnected or floating input does not cause the receiver to oscillate. when configured for differential operation (see figure 19 and table 57 ), the i nput receivers accommodate only ac - coupled input signals. the input receivers are capable of accepting ac - coupled lvds and 2.5 v or 3.3 v lvpecl signals. the receiver is internally dc biased to handle ac - coupled operation. note that the receivers do not ha ve an internal resistive termination (50 ? or 100 ?, for example). ref1_a p 1.8v ref1_an ref1_b p ref1_bn 1.8v 3.3v programmable 2.5v or 3.3v logic levels. 3.3v AD9531 25 24 28 27 12973-020 figure 19 . pll1 reference clock receivers when configured for single - ended operation (see figure 19 and table 57 ), the ref1_ap and/or ref1_bp inputs have a user - programmable input voltage range of 3.3 v or 2.5 v. these pins possess an internal bias of 1. 65 v or 1.25 v (for 3.3 v and 2.5 v operation, respectively) via an internal resistor of approximately 4 6 k?. this configuration allows either dc coupling (typical) or ac coupling, with ac coupling preferred for 3.3 v operation. note that, when operating i n single - ended mode , the ref1_an and/or ref1_bn pins are nonfunctional; therefore, connect these pins directly to ground to avoid parasitic coupling of stray signals. pll1 reference frequ ency scaling the frequency of the active reference is scalable via th e r1 bits in register 0x 0104 and register 0x 0105 ( see table 58 ). this configuration allows the user to scale the reference frequency to satisfy the input range of the pfd. the frequency appearing at the input to the pfd of pll1 depends on the frequency o f the active reference (ref_1a or ref_1b) , scaled according to the following criteria: w hen r1 = 0 , the pfd frequency is twice the active reference frequency. that is, the 2 frequency multiplier is active. a value of 1, 2 , or 3 for r1 effectively bypasses the divider , making the pfd frequency the same as the active reference frequency. the rem aining values of r1 (4 to 4095) rev. 0 | page 34 of 88
data sheet AD9531 cause the pfd frequency to be the active reference frequency , divided by the value of r1. note that, when the 2 frequency multiplier is in use , the active reference signal must have a duty cycle close to 50%. otherwise, spurious artifacts ( or harmonics) may propagate through the signal path and appear at the output of pll1. pll1 phase frequency detector ( pfd) and charge pumps the pfd de termines the phase difference between the edges of the reference divider output and the edges of the feedback divider output. the maximum operating frequency of the pfd depends on the operating mode of the pll (see tab le 39) . table 39. maximum pfd rate for pll1 pll mode maximum pfd r ate (mhz ) integer -n 260 fractional -n 50 the charge pump circuit provides two pulse - width modulated output signals: an up pulse and a down pulse . these up/down pulses drive t he charge pump circuit. the instantaneous phase error determines the amount of charge delivered from the charge pump to the loop filter. t he closed - loop of the pll tends to drive the frequency and phase difference between the two pfd input signals toward zero. the AD9531 pll1 contains two separate charge pumps. one is a 1.8 v charge pump that control s the internal vco , and the other is a 3.3 v charge pump that drive s an external loop filter and vcxo ( the vcxo is 3.3 v compliant) . the 1.8 v charge pump current is not user - programmable because the pll1 control logic automatically sets the 1.8 v charge pump current as required. the 3.3 v charge pump, however , is user - programmable in increments of 625 a up to 5 ma via register 0x 0101 , bits [ d 4: d 2]. pll1 loop filter a loop filter affects the dynam ic characteristics (for example, lock time and stability) of a pll. when using an external vcxo, a completely external loop filter is required , as shown in figure 12 . conversely, when using the internal vco, the integrated loop filter of the AD9531 requires only a single external capacitor or a series r c combination connected between the lf pin and the ldoreg1 pin . for a summary of t he loop filter component values, see table 40. table 40. pll1 loop filter component values component loop 1 loop 2 loop 2 wide bandwidth r z 2.75 k ? 0 ? 0 ? r z ( external ) 1 k ? application specific 1 k ? c z ( external ) 2.7 nf application specific 2.7 nf c p 50 pf 50 pf 50 pf r3 2 k ? 2 k ? 285 ? c3 50 pf 50 pf 50 pf the pll1 loop 1 configuration relies on dynamic charge pump current control to maintain a constant loop bandwidth of approximately 50 khz, independent of the value of the n1a feed - back divider. the loop 2 and internal loop 4 configurations, however, use static charge pump current; therefore, the bandwidth depends on the feedback divider value. pll1 internal vco pll1 incorporates a low phase n oise , lc tank vco. this vco has 256 f requency bands spanning from 3500 m hz to 3 9 00 ghz. at power - up, a vco calibration cycle begins; this cycle selects the proper band based on the feedback divide r value (see the pll1 internal vco calibration section). the internal vco has an integrated ldo linear voltage regulator t hat isolates the vco from possible external supply voltage variations. the regulated ldo voltage ap pears at the ldoreg1 pin. to ensure stability, connect a 220 nf capacitor between this pin and ground . this ldo uses anycap? technology from analog devices, inc., making it insensitive to the type capacitor used for bypassing purposes. note that using the ldoreg1 pin to power an external circuit may compromise vco performance. pll1 vco divider (m1 ) the internal vco op erates in the 4 ghz range; this range is too high to clock the output channel dividers. the purpose of the m1 divider is to scale d own the internal vco frequency to an acceptable range for the output channel dividers. the m1 divider is programmable over a range of 3 to 11. under normal operation, the re is no need for the user to reset the m1 divider manually because the vco calibration process (see the pll1 internal vco calibration section ) au tomatically resets m1. however, when the user wants to change the m1 divider without recalibrating the pll1 vco, the user must execute the following sequence: 1. reset the m1 divider (write register 0x010f , bits [ d 3: d 0] = 0xf ) . 2. issue an input/output update (write register 0x0005, bit d 0 = 1 ) . 3. program the new m1 divider value . 4. issue an input/output update (write register 0x0005, bit d 0 = 1 ). pll1 external vcxo i nput (rfin1 _x ) the rfin1_p and r fin1_n pins are configurable in both differential and single - ended operation via register 0x 0101, bits [ d 1: d 0]. in differential mode, t he pins are internally self biased, and the input signal is ac - coupled via capacitors. in single - ended mode , only one input is operational, either rfin1_p or rfin1_n, but not both (see table 57 for details). note t hat t he single - ended receivers possess hysteresis and have no internal bias. rev. 0 | page 35 of 88
AD9531 data sheet rfin1_ p rfin1_n 1.8v 2.5k 2.5k 0.68v AD9531 3.3v t olerant 33 34 12973-021 figure 20 . rfin1_p/ rfin1_ n equivalent input circuit when using an external vcxo with a 3. 3 v cmos single - ended output, however, it is best to use the differential input mode to minimize duty cycle distortion. for more information , see the interfacing to the rfin1_ x pins section under applications information . pll1 clock distribut ion pll1 output groups th e clock distribution section exi sts as three groups of outputs, group 1a, group 1b , and group 1c, with each group having several output drivers that share a channel divider. group 1a consists of output drivers for out1_0 through out1_3 and the d1a channel divider . group 1b consists of output drivers for out1_4 through out1_7 and the d1b channel divider. group 1c consists of output drivers for out1_8 , out1_9 , and the d1c channel divider . pll1 channel dividers the three channel dividers d1a, d1b, and d1c are program - mable from a factor of 0 to a factor of 255 , corresponding to divide ratios ranging from 1 to 256. note that each channel divider has duty cycle correction for odd divide ratios. pll1 output power - down the ten output drivers (out1_0 x through out1_9 x ) have independent p ower - down control via the spi registers. ea ch driver has a dedicated power - down bit in its appropriate control register. in addition, setting all three logic mode bits of a particular driver to logic 0 power s down the output driver. no te that powering down all the drivers in a group also powers down the channel divider associated with that group. for example, powering down output drivers out1_4 x through out1_7 x automatically powers down d1b. pll1 output operating mode the user has indep endent control of the operating mode of each of the ten output channels via the logic mode bits for pll1 in the register map . table 41 summarizes the operating modes. fo r lvpecl applications, use hstl mode and ac - coupl e the output signal. table 41. pll1 output mode selection logic mode , bits [2:0] description 000 disable 001 hstl 010 undefined 011 undefined 100 1.8 v cmos, out1_xp active, out1_xn active 101 1.8 v cmos, out1_xp active, out1_xn disable d 110 1.8 v cmos, out1_xp disable d , out1_xn active 111 undefined pll1 output polarity when the user programs a particular output for 1.8 v cmos mode, the polarity of the driver associated with that output is also programmable (via the polarity bits for pll1 in the register map ). that is, the logical sense of the output pin, out1_xp or out1_xn , is invertible. table 42 summarizes the polarity options (normal vs. inverted) for both the positive and negative pins of the particular 1.8 v cmos output. table 42 . output polarity, 1.8 v cmos mode only polarity, bits [1:0] description 00 out1_xp normal, out1_xn invert ed 01 out1_xp normal, out1_xn normal 10 out1_xp invert ed , out1_xn invert ed 11 out1_xp invert ed , out1_xn normal pll1 output clock divider synchronization (sync) the sync function allows the user to control the reset of the channel dividers (d1x) so t hat t hey can be phase aligned with each other. upon assertion of a sync signal, the sync block holds the channel dividers r eset and disables the clock signals at their inputs. the clocks driving the channel dividers resume on the falling edge of the sync signal. therefore , the sync signal is a single, positive pulse with both edges necessary to perform output synchronization. after the sync block receives a falling edge , it allows the channel dividers to start up in a known state , even in the absence of an input clock. when using pll1 in any of the internal vco operating modes, the calibration complete and lock detect signals w ithin the contro l logic of pll1 gate the sync function (see the automatic output synchronization section). therefore, the output channel dividers do not synchronize until pll1 locks, a vco calibration sequence executes successfully, and a sync pulse occurs. m anually force a sync pulse by writing the following register sequence: 1. register 0x0100, bit d 2 = 1 to set the manual sync bit. 2. r egister 0x0005, bit d 0 = 1 to assert the input/output u pdate bit . 3. register 0x0100, bit d 2 = 0 to clear the manual sync bi t. 4. register 0x0005, bit d 0 =1 to ass ert the input/output update bit. rev. 0 | page 36 of 88
data sheet AD9531 note that , if assertion of a sync pulse occurs prior to the pll lock and the successful completion of the vco calibration, then synchronization of the channel dividers does not occur until both conditions are satisfied. oth erwise, the channel dividers synchronize coincident with the falling edge of the sync pulse. pll1 holdover mode and freerun mode pll1 holdover mode when the AD9531 enters holdover mode, whether invoked manually or automatically, a reset state is in effect for the pfd and charge pump (either the 1.8 v or the 3.3 v charge pump , per the prevailing loop configuration). this mode places the charge pump in a tristate cond ition , effectively freezing the state of charge on the capacitors in the loop filter (either internal or external per the prevailing loop configuration). by holding the current state of charge on the loop filter, the vco control voltage remains essentially constant, thereby holding the vco output frequency at the value it maintained upon entering holdover mode. although the vco frequency remain s constant under these conditions, it is subject to frequency drift caus ed by charge injection or bleed off, for ex ample, the capacitor leakage current or the charge pump leakage current . pll1 freerun mode the most important fact regarding freerun mode is that it only applies to the external loop configurations (loop 3 or external loop 4). when the device enters freer un mode, whether invoked automatically or manually, it operates much the same as it does in holdover mode. however, in this case the device only acts on the 3.3 v charge pump. i n addition to the charge pump entering a tristate condition, an internal resist or connects the lf pin to an internal voltage equal to half the 3.3 v supply. the internal resistor, combined with the tristate condition of the charge pump, e ffe ctively holds the vco control voltage at a constant 1.65 v. manual holdover mode /freerun mode f orce the device into holdover m ode at any time by setting the holdover bit (register 0x0102, bit d 6 ). note that, if one of the internal loop configurations is in effect, setting the freerun bit (register 0x0102, bit d 7 ) also forces holdover mode. be aware , however, that in this case , the pll1 freerun bit (register 0x0082, bit d 2) is true, even though the device is technically in holdover mode. f orce the device into freerun mode at any time (assuming an external loop configuration is in effec t) by setting the freerun bit (register 0 x0102, bit d 7 ). automatic holdover mode /freerun mode the AD9531 supports automatic transi tion to holdover mode when the enable auto hold bit (register 0x0102, bit d 1 ) is logic 1 and the freerun vs. holdover bit (regis ter 0x0102, bit d 2) is logic 0. an automatic transition to holdover happens when the appropriat e lor states of ref1_a and/or ref1_b occur. specifically, if the enable auto switch bit (register 0x0102, bit d 0 ) i s logic 0, the automatic transition to holdover occurs when the selected reference (see the manual reference selection section) indicates lor (ref1_a x or ref1_b x, as the case may be). however, if the enable auto switch bit is logic 1, then both ref1_a and ref1_b must indicate lor before an automatic transition to holdover occurs. automatic transition to freerun mode occurs in identically the same manner as an automatic transition to holdover, but only when an external loop configurat ion is in effect and both the enable auto hold bit and the f reerun vs . holdover bit are both logic 1 (register 0x 0102 , bits [ d 2: d 1]). pll1 reference selec tion manual and automa tic manual reference selection manual reference selection allows the user to control whether ref1_a or ref1_b is the active reference. manual control is possible via both hardware (the ref1_sel pin) and software (by means of the spi port , register 0x 0102, bits [ d 5: d 4]). hardware - based manual reference selection uses the ref1_sel pin to make ref1_a or ref1_b the active reference. logic 0 selects ref1_a , whereas logic 1 selects ref1_b. note that programming the device for automat ic reference switching via the enable auto switch bit disables the functionali ty of the ref1_sel pin. s oftware - based manual reference selection via the spi port uses the enable reference select and reference select bits of register 0x 0102. wh en the enable reference select bit is logic 0 , manual reference selection via the spi port is disabled. wh en the enable reference select bit is l ogic 1, the reference select bit selects ref1_a or ref1_b as the active reference: logic 0 selects ref1_a , whereas logic 1 selects ref1_b. note that manual reference selection via the spi port overrides the automatic reference selection function as well as manual reference selection via hardware using the ref1_sel pin. automatic reference selection automatic reference selection allows the device to select a r eference automatically based on the lor status of pll1 (see the loss of reference (lor) section). automatic reference selection is in eff ect when the e nable auto switch bit is logic 1. upon lor indication, the device decides whether to switch refere nces. if the active reference indicates lor and the alternate r eference does not, the device automatically switches to the alternate reference. otherwise, the currently selected reference remains the active reference. when an automatic reference switch occurs, the new reference becomes the active reference and the other the alternate refer ence, which allows the device to switch back and forth between the two re ferences as required . be aware, however, that manual ref erence selection via register 0x 0102 , bits [ d 5: d 4] overrides this automatic switching feature. rev. 0 | page 37 of 88
AD9531 data sheet note that the automatic reference switch feature is non revertive. for example, suppose that ref1_a is the active reference, but it s lor becomes active, which triggers a reference switch from ref1_a to ref1_b (assuming ref1_b does not indicate lor). this switch makes ref1_b the active reference. then, suppose ref1_a subsequently becomes available ( meaning its l or clears). at this point, instead of the device preferentially reverting to ref1_a, it retains ref1_b as the active reference until ref1_b indicates lor , whereupon a switch back to ref1_a occurs (assuming ref1_a does not indicate lor). pll1 internal vco calibration when loop 1 (integer or fractional - n mode), loop 2 , or the internal variant of loop 4 is in effect, the internal vco is subject to calibration. calibration centers the v co control voltage at the vco frequency established after the pll locks , al lowing the vco sufficient operating range to maintain lock over extremes of temperature and voltage (as long as the loop parameters do not change) . at power - up, the vco calibration sequence automatically executes , as long as the multifunction pins select a profile that includes a vco calibration command. otherwise, the use r must do so man - ually via the pll1 manual calibrate bit (bit d1 in register 0x0100). vco calibration requires the presence of a reference signal. therefore , assuming a signal is present a t the ref1_a and/or ref1_b inputs, the vco calibration controller awaits indication of a valid reference signal. note that , in the absence of a refere nce signal, the device remain s in vco calibration mode until a valid reference is present. validation of a n input signal initiates the vco calibration sequence, which allows the loop to lock and selects the appropriate vco frequency band. when the loop parameters change (a new reference frequency or different feedback divider value, for example) , it is necessa ry to manually initiate a vco calibration sequence. to accomplish this, write the following register sequence: 1. register 0x0100, bit d 1 = 0 clear s the manual calibrate bit. 2. register 0x0005, bit d 0 = 1 assert s the input/output update bit. 3. register 0x0100, b it d 1 = 1 set s the manual calibrate bit. 4. register 0x0005, bit d 0 = 1 assert s the input/output update bit. note that, when the internal variant of loop 4 is in effect, vco calibration requires special treatment. this is because the m1 and d1x dividers stop during vco calibration (a result of the automatic sync function imposed during calibration), which prevents the calibration circuitry from receiving the required feedback clock edges. therefore, the calibration controller detects that loop 4 is in effect and automatically switch es to the loop 1 configuration to perform the vco calibration sequence. upon completion of the calibration sequence, the calibration controller automatically restores the loop 4 configuration. note that , because the cal ibration controller uses the loop 1 configuration, the n1a divider is necessarily in the feedback path during the calibration sequence. therefore, the user must program the value of the n1a divider before initiating a calibration sequence in the loop 4 con figuration, such that n1a = m1 d1x that is , n1a must match the product of the m1 divider and the selected channel divider (d1a, d1b , or d1c , as assigned per the fixed delay bits of register 0x 0101 , bits [ d 6: d 5]). programming n1a to the correct value ensures the calibration controller sets the correct charge - pump current for the loop 4 configuration. note that , during a vco calibration sequence , the calibration controller holds the distribution section in sync mode (channel di viders reset and output drivers are static) until the calibration terminates. therefore, no output signals appear until the vco calibration sequence terminates as indicated by a logic 1 to logic 0 transition of the pll1 calibration in prog ress bit (registe r 0x0080, bit d 4 ). the vco calibration process requires approximately 172,000 cycles of the pfd to complete. therefore , the calibration time (t vco_cal ) depends on the input frequency to the pfd as follows: t vco_cal = pfd f 5 10 72 . 1 rev. 0 | page 38 of 88
data sheet AD9531 figure 21 shows a flowchart demonstrating a robust pll1 vco calibration procedure. the procedure terminates with an optional output synchronization sequence. in the flowchart , the terms cal_count a nd t imer represent variables in the software code that a programmer may use to implement the flow chart . start done cal_count = 0 write register 0x0100[d1] = 0 vco calibration pll1 recalibration loop pll1 lock detect polling loop vco cal. bit input/output update bit vco cal. bit input/output update bit write register 0x0005[d0] = 1 write register 0x0100[d1] = 1 write register 0x0005[d0] = 1 write register 0x0100[d2] = 1 distribution synchronization operation sync bit input/output update bit sync bit input/output update bit write register 0x0005[d0] = 1 write register 0x0100[d2] = 0 write register 0x0005[d0] = 1 cal_count = cal_count + 1 start timer: timer = 0 lock detect bit cal_count > 1 read register 0x0080[d0] = 1 timer > 100ms no no no yes yes yes pll1 failed calibration 12973-121 figure 21 . pll1 vco calibration flowchart rev. 0 | page 39 of 88
AD9531 data sheet pll1 - modulator the n1a feedback divider of pll1 has an accompanying third - order sdm that allows integer plus fractional frequency translation. this feature, however, only applies to the loop 1 configuration. the integer part of the feedback divider ratio is the n1a divider, whereas the fractional part depends on 20 - bit fractional and modulus values appearing in the n1a fractional register and the n1a modulus register , respectively (see table 58 ). the total feedback divi der ratio is expressed as modulus n1a fraction n1a n1a n1a total + = pll1 lock detector th e lock detector in pll1 is a digital frequency detector. it effectively averages the frequency difference between the feedback and reference inputs to the pfd over an interval spanning 2 16 pfd cycles and indicates a lock condition when the average difference is less than 32 ppm. therefore, the minimum time necessary to detect a lock condition (t ldet ) depends on the pfd frequency as follows: pfd ldet f t 16 2 = rev. 0 | page 40 of 88
data sheet AD9531 pll2 fixed interna l loo p fi l ter vco reference detec t or dld vdd2 ldet2/m2 ref2_n ref2_ p out2_0x r2 n2 m2 d2 a d2d d2b d2c r z c3 c p c z pfd charge pum p 2.4ghz t o 2.5ghz r3 out2_1x out2_2x out2_3x out2_4x out2_5x out2_6x out2_7x out2_8x out2_9x out2_10x out2_ 1 1x 12973-022 figure 22 . pll2 block diagram pll2 integer - n pll pll2 is a fully integrated integer - n pll that includes a vco and internal loop filter (see figure 22 ). pll2 has a single reference input supporting either a differential clock signal or a crystal resonator. pll2 has an output distribution section supporting twelve outputs segregated into fou r groups. each group has a dedicated channel divider , allowing the device to produce four different output frequencies simultaneously. pll2 reduces the reference input frequency (f ref ) via the r2 divider by an integer factor (see the pll2 reference divider (r2) section) , setting the frequency at the input to the pfd. r2 f f ref pfd = r2 is an element of the following set: {1, 2 ... 16}. the pll core scales the pfd frequency up by an integer multiple per the feedback divider, n2, yielding the vco frequency. f vco = f pfd n2 where n2 is an element of the following set: {20, 21 ... 255}. the vco divider, m2, and the channel dividers (d2x) produce the final output frequency, f out2 . d2 m2 f f vco out2 = f out2 is the frequency at out2_x . d2 is the channel divider (d2a, d2b, d2c, or d2d) associated with out2_x. m2 is an element of the following set: {3, 4 ... 11}. d2 is an element of the following set: {1, 2 ... 256}. by substitution, the o verall frequency translation is d2 m2 n2 r2 f f ref out2 = pll2 reference clock input (ref2_p/ ref2_ n) the differential receiver associated with the ref2_p and ref2_n pins has a 1.8 v supply. typically, the user drives the reference input with a differential signal compatible with 1.8 v logic levels. for applications with a 3.3 v cmos reference, see the driving ref2 or ref3 with 3.3 v cmos logic in the applications information section for more details. pll2 reference divid er (r2) the function of r2 is to reduce the reference frequency to a range suitable for the phase detector (125 mhz, maximum). r2 divides by an integer factor ranging from 1 to 16 (see table 63). pll2 pfd and charge pump the pll2 pfd determines the phase difference between the edges of the reference divider output and edges of the feedback divider output. the circuit provides two pulse - width modulated output sig nals: an up pulse and a down pulse . these up/down pulses drive t he charge pump circuit. the instantaneous phase error determines the amount of charge delivered from the charge pump to the loop filter. the closed - loop of the pll tends to drive the frequency and phase difference between the two pfd input signals toward 0 . the control logic associated with pll2 sets the charge pump current based on the value of the feedback divider, n2, to maintain a nearly constant loop bandwidth of 500 khz , nominal. rev. 0 | page 41 of 88
AD9531 data sheet pll2 l oop filter pll2 has a fully integrated loop filter. the loop filter components ( see table 43 ) establish the nominal operating parameters of a 500 khz closed - loop bandwidth and a 60 phase margin. because the control logic for pll2 adjusts the charge pump current based on n2, the bandwidth and phase margin remain relatively constant , regardless of the value of n2. table 43. pll2 loop filter component values component value c z 180 pf r z 7 k ? c p 12.5 pf r3 250 ? c3 2.5 pf pll2 vco pll2 incorporates a low phase noise , lc tank vco. this vco has 64 frequency bands spanning from 2350 ghz to 2510 ghz. at power - up, the vco calibration sequence automatically executes as long as the multifunction pins select a profile that includes a vco calibration command . otherwise, the user mu st do so manually via the pll2 manual calibrat e bit in the register map (bit d1 in register 0x0200 ) . vco calibration requires the presence of a reference signal. therefore , assuming a signal is present at the ref2 _x input, the vco calibration controller awaits indication of a valid reference signal. note that , in the absence of a reference signal, the device remain s in vco calibration mode until a valid reference is present. validation of an input signal initiates the vco calibration sequence, which allows the loop to lock and selects the appropriate vco freque ncy band. when the loop parameters change (a new reference frequency or different feedback divider value, for example) , it is necessary to manually initiate a vco calibration sequence. to accomplish this, write the following register sequence: 1. register 0x0 200, bit d 1 = 0 clear s the manual calibrate bit. 2. register 0x 0005 , bit d 0 = 1 assert s the input/output update bit. 3. register 0x 0200 , bit d 1 = 1 set s the manual calibrat e bit. 4. register 0x 0005 , bit d 0 = 1 assert s the input/output update bit. the vco calibration process requires approximately 800,000 cycles of the pfd to complete. therefore , the calibration time (t vco_cal ) depends on the input frequency to the pfd as follows: pfd cal vco f t 5 _ 10 8 = rev. 0 | page 42 of 88
data sheet AD9531 figure 23 shows a flowchart demonstrating a robust pll 2 vco calibration procedure. the procedure terminates with an optional output synchronization sequence. in the flow chart, the terms cal_count a nd t imer represent variables in the software code that a programmer may use to implement the flow chart . start done cal_count = 0 write register 0x0200[d1] = 0 vco calibration pll2 recalibration loop pll2 lock detect polling loop vco cal. bit input/output update bit input/output update bit input/output update bit vco cal. bit input/output update bit write register 0x0005[d0] = 1 write register 0x0200[d1] = 1 write register 0x0005[d0] = 1 write register 0x0200[d2] = 1 distribution synchronization operation sync bit sync bit write register 0x0005[d0] = 1 write register 0x0200[d2] = 0 write register 0x0005[d0] = 1 cal_count = cal_count + 1 start timer: timer = 0 lock detect bit cal_count > 1 read register 0x0080[d1] = 1 timer > 100ms no no no yes yes yes pll2 failed calibration 12973-123 figure 23 . pll2 vco calibration flowchart rev. 0 | page 43 of 88
AD9531 data sheet pll2 vco divider (m2) the internal vc o operates in the 2.4 ghz to 2.5 ghz range; this range is too high to clock the output channel dividers. the purpose of the m2 divider is to scale down the vco frequency to an acceptable range for the output channel dividers. the m2 divider is program - mable over a range of 3 to 11 via register 0x 0204 , bits [ d 3: d 0]. under normal operation, there is no need for the user to reset the m2 divid er manually because the vco calibration process (see the pll2 vco section) automatically resets m2. however, when the user wants to change the m2 divid er without recalibrating the pll2 vco, the user must execute the following sequence: 1. reset the m2 divider (write register 0x0204 , bits [ d 3: d 0] = 0xf) . 2. issue an input/output update (write register 0x0005, bit d 0 = 1). 3. program the new m2 divider value . 4. issue an input/output update (write register 0x0005, bit d 0 =1) . pll2 feedback divide r (n2) the n2 feedback divider is programmable over a useable ra nge of 13 to 255 via register 0x 0203 , bits [ d 7: d 0]. n2 sets the frequency multiplication factor from the input of the pfd input to the output of the vco. pll2 clock distribut ion pll2 output groups the clock distribution section exists as three groups of outputs (group 2a, group 2b, group 2c , and group 2d) , with each group havin g several output drivers that share a channel divider. group 2a consists of the d2a channel divider and the output drivers for out2_0 and out2_1. group 2b consists of the d2b channel divider and the output drivers for out2_2 through out2_4. g roup 2c consis ts of the d2c channel divider and the output drivers for out2_5 through out2_7. group 2d consists of the d2d channel divider and the output drivers for out2_8 and out2_11. pll2 channel dividers the four channel dividers (d2a, d2b, d2c , and d2d) are programmable from 0 to 255 , corresponding to the divide ratios of 1 to 256. note that each channel divider has duty cycle correction for odd divide ratios. pll2 output power - down the twelve output drivers (out2_0 through out2_11) have indepen dent power - d own control via the spi registers. ea ch driver has a dedicated power - down bit in its appropriate control register. in addition, setting all three logic mode bits of a particular driver to logic 0 power s down the output driver. note that poweri ng down all the drivers in a group also powers down the channel divider associated with that group. for example, powering down output drivers out2_2 x through out2_4 x automatically powers down d2b as well. pll2 output mode the user has independent control o f the operating mode of each of the twelve output channels via the logic mode bits for pll2 in the register map . table 44 summarizes the operating mode s. u se hstl mode and ac - couple the output signal for lvpecl applications . table 44. pll2 output mode selection logic mode [2:0] description 000 disable 001 hstl 010 undefined 011 undefined 100 1.8 v cmos, out2_xp active, out2_xn active 101 1.8 v cmos, out2_xp active, out2_xn disable d 110 1.8 v cmos, out2_xp disable d , out2_xn active 111 undefined pll2 output polarity when programming a particular output for 1.8 v cmos mode, the polarity of the driver associated with that output is also programmable (via the polarity bits for pll2 in the register map ). that is, the logical sense of the output pin, out2_xp or out2_xn , is invertible. table 45 summarizes the polarity options (normal vs. inverted) for both the positive and negative pins of the particular 1.8 v cmos output. table 45. output polarity, 1.8 v cmo s mode only polarity , bits [1:0] description 00 out1_xp normal, out1_xn invert ed 01 out1_xp normal, out1_xn normal 10 out1_xp invert ed , out1_xn invert ed 11 out1_xp invert ed , out1_xn normal pll2 output clock divider synchronization the sync function allows the user to control the reset of the channel dividers (d2x) so that they can be phase aligned with each other. upon assertion of a sync signal, the sync block holds the channel dividers reset and disables the clock signals at their inputs. the clocks driving the channel dividers resume on the falling edge of the sync signal. therefore , the sync signal is a single, positive pulse with both edges necessary to perform output synchronization. after the sync block receives a falling edge , it allows the channel dividers to start up in a known state , even in the absence of an input clock. rev. 0 | page 44 of 88
data sheet AD9531 the sync function is gated by the calibration complete and lock detect signals within the control logic of pll2 (see the automatic output synchronization section). therefore, the output channel dividers do not synchronize until pll2 locks, a vco calibration sequence executes successfully, and a sync pulse occurs. the user can manually force a sync pulse by writing the following register sequence: 1. register 0x0200, bit d 2 = 1 set s the manual sync bit. 2. register 0x 0005 , bit d 0 = 1 assert s the input/output update bit. 3. register 0x 0200 , bit d 2 = 0 c lear s the manual sync bit. 4. register 0x 0005 , bit d 0 = 1 assert s the input/output update bit. note that , if assertion of a sync pulse occurs prior to the pll lock and the successful completion of the vco calibration, synchronization of the channel dividers does not occur until both conditions are satisfied. otherwise, the channel dividers synchronize coincident with the falling edge of the sync pulse. rev. 0 | page 45 of 88
AD9531 data sheet pll3 ref3_n vdd3 ref3_ p pfd vco 720mhz t o 805mhz vco 720mhz t o 805mhz fixed interna l loo p fi l ter r zb c3 b c pb c zb r3b fixed interna l loo p fi l ter r za c3 a c p a c za r3 a charge pum p dlda charge pum p dldb ldet3/m3 dldb out3_1x out3_0x r3 a 2 n3 a d3b d3 a n3b dldb 2 a r3b 2 lor2 moni t or pll3 a pll3b 2b pfd 2 12973-023 figure 24 . pll3 block diagram pll3 integer - n pll pll3 consists of two, cascaded integer - n plls (pll3a and pll3b), each with a loop bandwidth in the range of approximately 2 mhz. a detailed block diagram of pll3 is shown in figure 24 . pll3 reference clock input (ref3_p/ ref3_ n) the differential receiver associated with the ref3_p and ref3_n pins has a 1.8 v supply. typically, the user drives the reference inp ut with a differential signal compatible with 1.8 v logic levels. for applications with a 3.3 v cmos reference, see the driving ref2 or ref3 with 3.3 v cmos logic section in applications information for more details. the pll3 reference clock input also supports direct connection to a crystal resonator. this feature is in effect wh en the xtal amp lifier bit (register 0x0300, bit d 4 ) is log ic 1. for applications using a crystal resonator at the reference clock input, see the using ref2 or ref3 with a crystal resonator section in applications information for more details. pll3 input frequency scaling the input frequency applied at ref3 is scalable via r3a per register 0x 0301 , bits [ d 3: d 0] (see table 69 ). this feature allows the user to scale the reference frequency to satisfy the input range of the pfd. the available frequency scaling f actors are as follows: 2, 1, 2/3 , 1/2, 1/3, 1/4, 1/6, and 1/8 . programming register 0x 0301, b its [ d 3: d 0] with a value of 0 disables in the input reference section. w hen using the 2 frequency multiplier in the input reference section (a frequency s cale factor of either 2 or 2/3), the ref3 signal must have a duty cycle close to 50%. otherwise, spurious artifacts (harmonics) may propagate through the signal path and appear at the output of pll3. pll3 pfd and charge pumps the pfd determines the phase d ifference between the edges of the reference divider output and the edges of the feedback divider output. the circuit provides two pulse - width modulated output signals: an up pulse and a down pulse . these up/down pulses drive t he charge pump circuit. the i nstantaneous phase error determines the amount of charge delivered from the charge pump to the loop filter. the closed - loop of the pll tends to drive the frequency and phase difference between the two pfd input signals toward 0 . the control logic associate d with pll3a and pll3b sets the respective charge pump current based on the value of the rev. 0 | page 46 of 88
data sheet AD9531 feedback divider s (n3a or n3b) to maintain a nearly constant loop bandwidth of 2 mhz, nominal. pll3 loop filters the loop filters associated with pll3a and pll3b are identical and have a third - order response characteristic. the control logic associated with pll3a and pll3b selects the appropriate comp - onent values of the respective loop filter based on the value of the respective feedback divider (n3a and n3b). this, i n con - junction with control of the respective charge pump current , yields a nearly constant loop bandwidth. that is, the closed - loop bandwidth of pll3a and pll3b is a function of the value of n3a and n3b, respectively, per table 46. table 46. pll3a/ pll3 b closed - loop bandwidth n3a, n3b 1 nominal closed - l oop bandwidth (mhz) less than 24 3.5 24 to 47 1.75 greater than 47 1.0 1 table 46 shows that, based on the value of the divider, n3a affects the loop bandwidth of pll3a and n3b affects the loop bandwidth of pll3b. pll3 vco s the vcos associated with pll3a and pll3b are identical and have a frequency range of 745 mhz to 805 mhz. each has a nominal gain of 750 mhz/v. pll3 feedback divide rs the feedback dividers associated with pll3a and pll3b (n3a and n3b, respectively) ar e identical , with divi de ranges according to register 0x 0302 and register 0x 0304 (see table 69 ) . program - ming a value of 0 bypasses the associated pll . therefore, when n3a = 0 , the scaled reference input frequency appears at the input to r3b and when n3b = 0 , the output frequency of the r3b divider appears at the input to the d3a and d3b channel dividers. pll3b reference divi der (r3b) the r3b reference divider is b etween pll3a and pll3b. r3b scales the output frequency of the vco from pll3a down to a range suitable for the pfd of pll3b . the integer factor, r3b, is variable via register 0x 0303 , bits [ d 7: d 0] , per table 69. pll3 clock distribut ion channel dividers the two channel dividers (d3a and d3b) are programmable , providing divide ratios from 1 to 16 (see table 70 and table 71 for details). note that each channel divider has a fixed divide by 2 divider at its output. therefore , the overall channel divide ratio is always even and spans a range of 2 to 32. the channel dividers power down when their associated output drivers power down. output clock divider synchronization the sync function allo ws the user to control the reset of the channel dividers (d3x) so that they can be phase aligned with each other. upon assertion of a sync signal, the sync block holds the channel dividers reset and disables the clock signals at their inputs. the clocks dr iving the channel dividers resume on the falling edge of the sync signal. therefore , the sync signal is a single, positive pulse with both edges necessary to perform output synchronization. after the sync block receives a falling edge , it allows the channe l dividers to start up in a known state even in the absence of an input clock. the sync function is gated by the lock detect signals within the control logic of pll3 (see the automatic output synchronization section) . therefore, the output channel dividers do not synch - ronize until pll3a and pll3b locks and a sync pulse occurs. the user can manually force a sync pulse by writing the following register sequence: 1. register 0x 03 00, bit d 2 = 1 set s the manual sync bit. 2. register 0x 0005 , bit d 0 = 1 assert s the input/output update bit. 3. register 0x 0300 , bit d 2 = 0 clear s the manual sync bit. 4. register 0x 0005 , bit d 0 = 1 assert s the input/output update bit. note that , if assertion of a sync pulse occurs prior to pll3 lock, synchronization of the channel dividers does not occur until the lock condition is satisfied. otherwise, the channel dividers synchronize coincident with the falling edge of the sync pulse. out 3_0 driver out3_0 utilizes a cmos driver, which normally functions as an output clock signal for pll3 and is capable of 1.8 v or 3.3 v cmos logic lev els as determined by register 0x0306, bit d 3 . in addition to controlling the output logic levels, the user also has control over the logical sense of out3_0, whi ch is invertible via register 0x0306, bit d 1 . furthermore, the out3 _0 driver has independent power - dow n control via register 0x0306, bit d 0 . out3_0 may function as an optional second lor pin, as well ( see the loss of reference (lor) section). note that , when using out3_0 as an lor pin , register 0x0306, bits[ d 3: d 0] are ineff - ective. out3_1 driver out3 _1 has multiple output driver operating modes , as shown in table 47 (see register 0x 0308 , bits [ d 6: d 3]). these modes include hstl, lvds , and 1.8 v or 3. 3 v cmos mode . f or lvpecl applications, use hstl mode and ac - couple the output signal. rev. 0 | page 47 of 88
AD9531 data sheet table 47. out3_1 output mode s logic mode , bits [3:0] description 0000 disable d 0001 hstl 0010 lvds 0011 undefined 0100 1.8 v cmos, out3_1p active, out3_1n active 0101 1.8 v cmos, out3_1p active, out3_1n disable d 0110 1.8 v cmos, out3_1p disable d , out3_1n active 0111 to 1011 undefined 1100 3.3 v cmos, out3_1p active, out3_1n active 1101 3.3 v cmos, out3_1p active, out3_1n disable d 1110 3.3 v cmos, out3_1p disable d , out3_1n active 1111 undefined when the user programs out3_1 for 1.8 v or 3.3 v cmos mode, the polarity of the driver is also programmable (via the polarity bits for pll3 in the register map ). that is, the logical sens e of the output pin, out3_1p or out3_1n , is invertible. table 48 summarizes the polarity options (normal vs. inverted). table 48 . output polarity, 1.8 v or 3.3 v cmos only polarity , bits [1:0] description 00 out3_1p normal, out3_1n invert ed 01 out3_1p normal, out3_1n normal 10 out3_1p invert ed , out3_1n invert ed 11 out3_1p invert ed , out3_1n normal furthermore, the out3_1 driver has independent power - down control via register 0x0308, bit d 0 . rev. 0 | page 48 of 88
data sheet AD9531 additional features power - o n reset (por) applying power to the AD9531 causes an internal power - on reset (por) event. the por event expires approximately 20 ms after the supply voltages reach 80% of their nominal value. the por event allows the device to initialize to a known state at power - up by initiating a rom load sequence (see the rom profiles section). note that the por event is critical to the operation of the multifunction pins. rom profiles the AD9531 has an integrated rom partitioned into 64 groups. each group constitutes a rom profile. each rom profile stores data that maps to particular spi registers and establishes the register default values. that is, the register default values depend on the current rom profile se lection. therefore, the rom label for the default value is in the register map for those registers mapped to the rom. at power - up, one of the first 1 6 rom profiles is loaded into the register map per the multifunction pins (see the multifunction pins (ldet1/m1, ldet2/m2, ldet3/m3, lor/m4) section f or more information) . however, the user can select any one of the 64 possible rom profiles by writing the desired profile value ( from 0 to 63) into register 0x 000e , bits [ d 5: d 0] (this register does not require an input/output update). writing to regist er 0x 000 e results in an immediate download of the rom profile contents into the register map and a reset of all plls. this reset means that each pll must be calibrated and synchronized (as applicable), unless the rom profile contains the requisite calibrate and sync commands. a listing of the register default values associated with each rom profile appears in the rom profile data section. furthermore, reading register 0x 000e allows the user to obtain the index value of the most recently loaded rom profile. multifunction pins ( ldet1/m1, ldet2/m2, ldet3/m3, lor/m4) during a por event, the ldet1/m1, ldet2/m2, ldet3/m3 , and lor/m4 pins function as inputs and const itute four rom profile select pins. the logic level on these pins during the por ev ent constitute s a 4 - bit binary word, m4 - m3 - m2 - m1, that selec ts one of the first 16 rom profiles , with m4 denoting the most sig nificant bit (msb) and m1 the least significant bit (lsb) . for example, during a por event, if the logic level on the pins, m4 - m3 - m2 - m1, is 0 - 1 - 0 - 0, respectively, then the AD9531 automatically loads rom profile 4. upon expiration of the po r event, the multifunction pins revert from mx inputs to ldetx and lor outputs. note that, when the ldetx and lor pins function as output signals, each pin is independently capable of 1.8 v or 3.3 v cmos logic levels. the output logic level for each pin depends on its associated 3.3 v mode bit in register 0x 0083 and register 0x 0084. when configuring these multifunction pins for 3.3 v operation, the pins make use of a booster circuit that generates 3.3 v from internally available 1.8 v supply domains. this generation has an impact on the 3.3 v operating mode of the lor/m1 pin in particular , as it requires pll2 to be active (powered up). the reason for this requirement is that the lor/m1 pin uses the internal 1.8 v supply domain associa ted with pll2. therefore , powering down pll2 shuts down the 1.8 v source that supplies the booster circuit of the lor/m1 pin. furthermore, when operating the lor or ldetx pins in 3.3 v mode , it is best to program the logical sense of the pin such that it i s normally in a logic 0 state. that is, when using the lor pin in 3.3 v mode, program the pin to produce logic 0 during normal operation (when an lor condition does not exist). likewise, when using the ldetx pins in 3.3 v mode, program them to produce logi c 0 during normal operation (when a lock condition exists). using the mx pins w ith 1.8 v, 3.3 v , or 1.5 v cmos logic a functional diagram of a representative mx pin is shown in figure 25 . during a por event (see the power - on reset (por) section), s1 is in the por position, which connects each mx pin to its own internal 1.8 v cmos receiver. after a por event, s1 is in the norm position, which connects each mx pin to its own internal cmos driver (capable of either 1.8 v or 3.3 v logic levels , per register 0x 0083 and register 0x 0084). ther e fore , except for the brief interval of time during a por event, the mx pins ope rate with s1 in the norm position, which constitutes normal device operation. por norm mx AD9531 1.8v s1 12973-024 figure 25 . functional diagram of an mx pin see the interfacing to the multifunction pins section in the applications information section for details on interfacing the mx pins to 1.8 v, 3.3 v , or 1.5 v cmos logic. rev. 0 | page 49 of 88
AD9531 data sheet loss of reference (l or) each of the plls within the AD9531 (pll1, pll2 , and pll3) is capable of lor detection. the lor detectors effectively report the absence of a reference clock or a reference clock with a significantly low frequency. lor detection figure 26 is a functional diagram of an lor detector. each reference input (ref) has a dedicated lor detector. the lor detectors consist primarily of a pair of edge detectors and timers , with the timers having a nominal period of 500 ns. there are two important features regarding the lor detectors: ? lor is not a latched status signal (it is memoryless) . ? lor is asserted following any of the four indicated reset events and is not deasserted until the lor detector detects the input signal (ref) . rising edge detec t or f alling edge detec t or up ref down s t art clear s t art clear preset preset lor timeout timeout edge detector 83'2:17,0(5v '2:1837,0(5v por rom profile load register 0x0004 [d4] register 0x0000 [d5] 12973-025 figure 26 . lor detector the edge detector independently monitors both the rising and falling edges of the ref signal. each rising edge generates an up pulse and each falling edge a d own pulse. the up and down pulses trigger the start and clear inputs to the two timers. the up / down timer effectively monitors the positive half cycles of ref, while the down / up counter effectively monitors the negativ e half cycles of ref. if any positive or negative half cycle of ref extend s beyond the nominal period of the associated timer (~500 ns), the timer times out resulting in the assertion of lor. lor status the lor status is available via the spi port, the lor/m4 pin, as well as optionally via the out3_0 pin by making any of the bits in register 0x 0085 , bits [ d 4: d 0] bits logic 1. spi port indication of lor for eac h pll is available via register 0x 0081. note that , in the case of pll1, the lor status of both ref1_a and ref1_b is available , regardless of which reference is the active reference. the identity of the active refere nce is available via register 0x0082, bit 0, where logic 0 indicates ref1_a as the active referen ce, and l ogic 1 in dicates ref 1_b as the active reference. the lor/m4 pin provides a hardware indication of the composite lor status of the device. there are five possible lor indications as follows : ? ref1_a lor ? ref1_b lor ? ref1 a ctive lor ? ref2 lor ? ref3 lor ref1_a lor, ref1_b lor , and ref1 active lor indicate the lor status of pll 1. specifically, ref1_a and ref1_b lor indicate the lor state of the designated reference, even if the designated reference is not the active reference. alternatively , ref1 active lor indicates the lor state of the active reference (ref1_a or ref1_b as app licable). ref2 lor indicates the lor state of pll2. ref3 lor indicates the lor state. note that pll3 is a cascade of two plls. the first of the two plls in the cascade is the only pll that provides lor indication. pin indication of lor is composite in that any combination of t he five possible lor indications previously noted can be logically ord via register 0x 0084 , bits [ d 4: d 0] and register 0x 0085 , bits [ d 4: d 0]. register 0x 0084 controls t he lor/m4 pin, while register 0x 0085 c ontrols the out3_0 pin. because of the logical or functionality of the lor bits, when all the lor bits of register 0x 0084 are logic 0 , the lor/m4 pin is tri state. making any of the bits logic 1, however, enable s the associated lor detector(s) to indicate a loss of reference in a logical or sense on the lor/m4 pin. in the case of register 0 x 0085, when all the lor bits are logic 0 , the out3_0 pin functions normally (that is, as an output of pll3). making any of the bits logic 1 enable s the associated lor detector(s) to indicate a loss of re ference in a logical or sense on the out3_0 pin. the lor/m4 pin indicates a logical true state for a loss of reference condition (per the lor bits of register 0x 0084). the actual logic level ( logic 0 or logic 1) depends on the invert bit (register 0x0084, bit d 5 ). when the invert bit is logic 0, an lor condition of true appears on the lor/m4 pin as logic 1, while a false condition appears as logic 0. when the invert bit is logic 1, an lor condition of tru e appears on the lor/m4 pin as logic 0, while a false condition appears as logic 1. the same is true for the out3_0 pin when it functions as an lor indicator, but with the invert bit located in register 0x0085, bit d 5 . rev. 0 | page 50 of 88
data sheet AD9531 pll lock detection ( ldet x ) pll1, pll2 , and pll3 each possess a built in digital lock detector (dld). pll1 has a frequency lock detector, whereas pll2 and pll3 have phase lock detectors. each dld senses the activity of its associated pfd to determine if the pll has acquired a lock con - diti on. the dlds possess hysteresis to minimize chatter in the lock detect signal as the loop acquires lock and crosses throug h an internal lock/unlock threshold. the dlds indicate a logical true state for a lock condition and a logical false state for an unlo ck condition. the actual logic level ( logic 0 or logic 1) a t an ldetx pin depends on the invert bit for that partic ular ldet indicator (register 0x 0083 , bit d 4, bit d 2, or bit d 0 ). when the invert bit is logic 0, a true dld condition appears on an ldetx pin as logic 1 , and a false condition appears as logic 0. when the invert bit is logic 1, a true dld condition appears on an ldetx pin as logic 0 , and a false condition appears as logic 1. furthermore, each of the ldetx pins may be set to 3.3 v logic (instead of 1.8 v log ic) by setting the appropriate 3.3 v mode bit in register 0x 0083. automatic output syn chronization the output distribution sections associated with pll1, pll2 , and pll3 can have their output channels synchronized so that all channels of a particular pll start producing clock signals at the same instant. the manual sync bit in the register map of a particular pll controls the synchronization function for that particular pll, as explained in the output synchronization secti on of the individual pll descriptions. however, output synchronization occurs automatically as the end result of a reset event , as defined by one of the following conditions : ? a por event ? a rom p rofile load ? a soft reset (register 0x0000, bit d 5 = 1) ? a hardware reset (register 0x0004, bit d 4 = 1) figure 27, figure 28 , and figure 29 contain flow diagrams showing the reset sequence for each pll. each seq uence begins with a reset event and terminates with the synchronization of the output channels. t he flowcharts shown in figure 27, figure 28 , and figure 29 apply only to a reset event. that is, i ndependent functions included within the flow of the reset sequence, such as calibrate or sync, are accessible via the programming registers , even after the reset sequence terminates. however, when accessed after the termination of the reset sequence, they behave as independent functions and do not follow the reset sequence flow. figure 27 shows the reset sequence for pll1. the ref1 pass and ref1 fail events apply to ref1 _ a and/or ref1 _ b , per the c ontents of register 0x 0084 , bits [ d 2: d 0]. these bits determine whether lor indicat ion is for ref1 _ a only, ref1 _ b only, or the active reference (ref1 _ a or ref1 _ b , per the reference switching controls). though not explicitly shown in figure 27 , the flow chart assumes implementation of the features in figure 21 t o ensure a more robust calibration sequence. figure 28 shows the reset sequence for pll2. the pll2 flowchart is similar to the pll1 flow chart shown in figure 27 , except for the absence of the external vcxo and fixed delay dependencies. though not explicitly shown in figure 28 , the flow chart assumes implementation of the features in figure 23 to ensure a more robust calibration sequence. figure 29 shows the reset sequence for pll3. the pll3 flowchart is similar to the pll2 flowchart shown in figure 28 , except for the absence of a calibration dependency. rev. 0 | page 51 of 88
AD9531 data sheet reset event por register 0x0000 [d5] = 1 register 0x0004 [d4] = 1 rom profile load lor1 ref1 p ass ca l request? yes no ca l done yes no ext vcxo? yes no pll1 lock w ait for ldet1 active outputs synchronized ca l w ait for ca l req ca l req yes no sync w ait for sync req sync req sync request? fixed del a y? 12973-026 figure 27 . pll1 reset sequence flowchart rev. 0 | page 52 of 88
data sheet AD9531 por register 0x0000 [5] = 1 register 0x0004 [4] = 1 rom profile load reset event lor2 ref2 p ass ca l done no ca l request? yes no ca l w ait for ca l req ca l req pll2 lock w ait for ldet2 active outputs synchronized yes no sync w ait for sync req sync req sync request? 12973-027 figure 28 . pll2 reset sequence flowchart por reg 0x0000 [d5] = 1 reg 0x0004 [d4] = 1 rom profile load reset event lor3 ref3 p ass no pll3 lock w ait for ldet3 active outputs synchronized yes no sync w ait for sync req sync req sync request? 12973-028 figure 29 . pll3 reset sequence flowchart rev. 0 | page 53 of 88
AD9531 data sheet serial control port the AD9531 serial control port is a flexible, synchronous, serial communications port that allows an easy interface to many industry - standard microco ntrollers and microprocessors. the serial port supports single or multiple byte transfers, as well as msb first or lsb first data transfer formats. note that the AD9531 serial control port does no t have dedicated input and output data pins, but only a single bidirectional sdio pin. the serial control port h as two types of registers: read only register and writable registers . read only registers are nonbuffered and ignore write commands. most writable registers are buffered ( also referred to as mirrored) and require an input/output update to transfer the new values from a temporary buffer on the chip to the actual register. to invoke an input/output update, write a 1 to the input/output update bit in register 0x 000 5, bit d 0 . because any number of bytes of data can be changed before issuing an update command, the update simultaneously enables all register changes that occur after any previous update. the serial port physical interface can operate from 1.8 v to 3.3 v based on the voltage provided on the dvdd_io pin. the default output drive strength is intended for 1.8 v operation, but a strength reduction option is possible via register 0x0004, bit d 1 . serial control port pin descriptions sclk (se rial data clock) is the serial shi ft clock. this pin is an input and synchronizes the serial control port read and write cycles. the serial port captures write data bits on the rising edge of sclk, and delivers read data bits on the falling edge of sclk. sdio (digital serial data input/output) is the serial data pin. cs (chip select bar) is an active low control that gates the read and write cycles. when cs is high, sdio is in a high impedance state (note that cs must not be left floating) . see the operation of the serial control port section for information on the use of the cs pin in a communication cycle. seria l contro l port sclk cs sdio 21 19 22 AD9531 12973-029 figure 30 . serial control port operation of the ser ial control port fr aming a communication cycle with cs the cs line gates the communication cycle (a write or a read operation). set cs to logic 0 to initiate a communication cycle. the cs stall high func tion is supported in modes where three or fewer bytes of data (plus instruction data) are transferred. bits[w1:w0] of the instruction word (16 bits) ( see table 50) must be set to 00, 01, or 10 (see table 49 ). in these modes, cs may temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. cs can go high on byte boundaries only and can go high during either part (instruction or data) of the transfer. during this period, the serial control port state machine enters a wait state until all data is sent. if the system controller decides to abort be fore the complete transfer of all the data, it is necessary to reset the state machine by either completing the remaining transfer or by returning the cs line low for at least one complete sclk cycle (but fewer than eight sclk cycles). a rising edge on the cs pin on a nonbyte boundary terminates the serial transfer and flushes the buffer. table 49 . byte transfer count w1 w0 bytes to transfer (excluding the 2 - byte instruction) 0 0 1 0 1 2 1 0 3 1 1 streaming mode in streaming mode ( bits [w1:w0] = 11), any number of data bytes can be transferred in a continuous stream. the register address is automatically incremented or decremented (see the msb/lsb first transfers section). at the end of the last byte to be transferred, set cs to logic 1 to end the stream mode. communication cycle instruction plus data there are two parts to a communication cycle with the AD9531 . the first part writes a 16 - bit instruction word into the AD9531 , coincident with the first 16 sclk rising edges. the instruction word (16 bits) ( see table 50 ) provides the AD9531 serial control port with information regarding the data transfer, which is the second part of the communication cycle. the instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting regist er address for the first byte of the data transfer. write operation if the instruction word is for a write operation ( bit i15 = 0), the second part is the transfer of data into the serial control port buffer of the AD9531 . the length of the transfer (1, 2, or 3 bytes or streaming mode) is indicated by two bits ( bits [w1:w0]) in the instruction word. the length of the transfer indicated by b its [w1:w0] does not include the 2 - byte instruction word. pul l cs high after each sequence of eight bits to stall the bus (except after the last byte, where t his ends the cycle). when the bus is stalled, the serial transfer resumes when cs is pulled low . stalling on nonbyte bounda ries resets the serial control port. note that stalling via the cs pin is not applicable in streaming mode. rev. 0 | page 54 of 88
data sheet AD9531 read operation if the instruction word is for a read operation ( bit i15 = 1), the next n 8 sclk cycles clock out the data from the address specified in the instruction word, where n = 1, 2, 3, or 4, as determined by bits [w1:w0]. in this case, the value of 4 is used for streaming mode, where four or more words are transfe rred per read. the serial port delivers the read back data to the sdio p in on the falling edge of sclk. by default, a read request reads the register value that is currently in use by the AD9531 . however, setting register 0x 000 4, bit d 0 = 1 causes the buffered registers to be read instead. the buffered registers are the registers that take effect during the next input/ output update. seria l contro l port sclk cs sdio 21 19 22 register buffers contro l registers AD9531 core register upd a te execute an input/output upd a te 12973-030 figure 31 . relationship between the se rial control port register buffers and the control registers instruction word (16 bits) the msb of the instruction word (see table 50 ) is r/ w , which indicates whether the instruction is a read or a write. the next two bits, w1 and w0, are the transfer length in bytes. the final 13 bits are the address bits ( address bits[ a12:a0]) , at which the read or write operation begins . for a write operation , the instruction word is followed by the number of bytes of data indicated by bits [w1:w0], which is interpreted according to table 49 . address bits [a12:a0] select the address within the register map t hat is written to or read from during the data transfer portion of the communication cycle. the AD9531 uses all of the 13 - bit address space . for multibyte transfers, this address is the starting b yte address. msb/lsb first transf ers the AD9531 instruction word and byte data can be msb first or lsb first. the default for the AD9531 is msb first. activate t he lsb first mode by setting register 0x 0 000, bit d 6 = 1 (an input/ output update is not required). immediately after writing register 0x0000, bit d 6 = 1, all serial control port operations are changed to lsb first order. when msb first mode is active, the instruction word and data bytes must occur in msb to lsb order. multibyte data transfers in msb first format start with an instruction word that includes the register address of the most significant data byte. subseque nt data bytes must follow in order from high address to low address. in msb first mode, the serial control port internal address gener - ator decrements for each data byte of the multibyte transfer cycle. when lsb first mode is active, the instruction word and data bytes must occur in lsb to msb order. multibyte data transfers in lsb first format start with an instruction word that includes the register address of the least significant data byte followed by multiple data bytes. in lsb first mode, the serial control p ort internal address generator increments for each data byte of the multibyte transfer cycle. in summary, for msb first (default) multibyte input/output operations, the AD9531 serial control port internal address generator decrements , whereas for lsb first multibyte input/output operations, it increments. furthermore, the serial port controller does not skip unused addresses for multibyte input/output operations . w rite the default value to a reserv ed register , or write l ogic 0 to unused registers. it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unused) registers. table 50. serial control port, 16 - bit instruction word, msb first msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 table 51 . definition of terms used in the serial control port timing diagrams (see figure 32 through figure 37 ) parameter description t s clk period of sclk t dv read data valid time ( the time from the falling edge of sclk to valid data on sdio) t ds setup time between data and the rising edge of sclk t dh hold time between data and the rising edge of sclk t s setup time between cs and sclk t h hold time between cs and sclk t high minimum period that sclk can be in a logic high state t low minimum period that sclk can be in a logic low state rev. 0 | page 55 of 88
AD9531 data sheet cs sclk don't care sdio a12 w0 w1 r/w a 1 1 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) d at a register (n C 1) d at a 12973-031 figure 32 . serial control port write msb first, 16 - bit instruction, two bytes data cs sclk sdio register (n) d at a 16-bit instruction header register (n C 1) d at a register (n C 2) d at a register (n C 3) d at a a12 w0 w1 r/w a 1 1 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don't care don't care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 12973-032 33 16 - t s don't care don't care w1 w0 a12 a 1 1 a10 a9 a8 a7 a6 a5 d4 d3 d2 d1 d0 don't care don't care r/w t ds t dh t high t low t sclk t h cs sclk sdio 12973-033 34 16 - d at a bit n C 1 d at a bit n cs sclk sdio t dv 12973-034 35 cs sclk don't care don't care 16-bit instruction header register (n) d at a register (n + 1) d at a sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a 1 1 a12 d1 d0 r/w w1 w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 12973-035 36 16 - sclk sdio t high t low t sclk t s t ds t dh t h bit n bit n + 1 cs 12973-036 37 rev. 0 | page 56 of 88
data sheet AD9531 register map registers are generic with normal read/write capabilit y unless otherwise noted in the option column (opt.) as follows: ? a means automatically cleared . ? b means buffered register (requires an input/output u pdate) . ? r means read only . ? x means execute rom load on register write . ? n/a means not applicable. the user must avoid writing to register addresses not listed in table 52 . such undocumented addresses may have reserved functionality and writing to them may cause abnormal device behavior. bits labeled unused have n o associated physical hardware; therefore, writi ng to these bits has no effect . bits label led reserved may have associated hardware. when writing to reserved bits , use th e values in the default column (def.) . in the default column, ? values are hexadecimal , unless otherwise noted. ? values with an r prefix indicate that the default values originate from the rom and the digits following the r prefix indicate the rom indices associated with the register bits (see the rom profile data section). ? the s pec default value (register 0x 0004) is logic 0 for all bits except the d1 bit , which uses rom default r639 (see the rom profile data section). ? the p in default value (register 0x 000e) indicates that the multifunction pins set the de fault value as described in the multifunction pins (l det1/m1, ldet2/m2, ldet3/m3, lor/m4) section. table 52 . register map reg . addr . (hex) opt . name d7 d6 d5 d4 d3 d2 d1 d0 def . serial port control registers 0 x 0000 n/a spi control unused lsb first soft reset unused 0x 00 0 x 0004 n/a serial port options unused hardware reset unused reduce spi strength read buffer register spec 0 x 0005 a i nput/output (i/o) update unused i/o update 0x 00 device and rom profile identification registers 0x 000a r device id device id, bits [31:24] 0x 10 0x 000b r device id, bits [23:16] 0x 00 0x 000c r device id , bits [15:8] 0x 08 0x 000d r device id, bits [7:0] 0x 00 0x000e x profile reserved rom profile, bits [5:0] pin status registers 0x 0080 r status reserved pll2 calibration in progress pll1 calibration in progress reserved pll3 lock detect pll2 lock detect pll1 lock detect n/a 0x 0081 r unused ref3 lor ref2 lor ref1b lor ref1a lor n/a 0x 0082 r unused reserved pll1 freerun pll1 holdover pll1 active reference n/a ldet/lor control registers 0x 0083 b ldet reserved ldet3 3.3 v mode ldet3 invert ldet2 3.3 v mode ldet2 invert ldet1 3.3 v mode ldet1 invert rom 0x 0084 b lor reserved 3.3 v mode invert ref3 lor ref2 lor active ref1 lor ref1b lor ref1a lor rom 0x 0085 b lor2 reserved 3.3 v mode invert ref3 lor ref2 lor active ref1 lor ref1b lor ref1a lor rom pll1 registers 0x 0100 b pll1 general registers unused reserved manual sync manual calibrate power - down rom 0x0101 b enable m1 d uring vco c al ibrati on fixed delay, bits [1:0] 3.3 v charge pump current, bits [2:0] external oscillator (vcxo) mode, bits [1:0] rom 0x 0102 b freerun holdover enable reference select reference select wide bandwidth mode freerun vs. holdover enable auto hold enable auto switch rom 0x 0103 b vco calibration reset ref1b input mode , bits [1:0] ref1b power - down reserved ref1a input mode , bits [1:0] ref1a power - down rom rev. 0 | page 57 of 88
AD9531 data sheet reg . addr . (hex) opt . name d7 d6 d5 d4 d3 d2 d1 d0 def . 0x 0104 b pll1 frequency translation registers r1 , bits [7:0] rom 0x 0105 b unused r1 , bits [11:8] rom 0x 0106 b n1a , bits [7:0] rom 0x 0107 b n1a fraction , bits [7:0] rom 0x 0108 b n1a fraction , bits [15:8] rom 0x 0109 b reserved n1a fraction , bits [19:16] rom 0x 010a b n1a modulus , bits [7:0] rom 0x 010b b n1a modulus , bits [15:8] rom 0x 010c b reserved n1a modulus , bits [19:16] rom 0x 010d b n1b , bits [7:0] rom 0x 010e b unused n1b , bits [11:8] rom 0x 010f b unused m1 , bits [3:0] rom 0x 0110 b d1a d1a , bits [7:0] rom 0x 0111 b out1_0 unused logic mode , bits [2:0] polarity , bits [1:0] power - down rom 0x 0112 b out1_1 unused logic mode , bits [2:0] polarity , bits [1:0] power - down rom 0x 0113 b out1_2 unused logic mode , bits [2:0] polarity , bits [1:0] power - down rom 0x 0114 b out1_3 unused logic mode , bits [2:0] polarity , bits [1:0] power - down rom 0x 0115 b d1b d1b , bits [7:0] rom 0h0116 b out1_4 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x0117 b out1_5 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x0118 b out1_6 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x0119 b out1_7 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x011a b d1c d1c [7:0] rom 0x011b b out1_8 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x011c b out1_9 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom pll2 registers 0x 0200 b pll2 general registers unused reserved xtal amp lifier reserved manual sync manual calibrate power - down rom 0x 0201 b unused manual charge pump current charge pump current, bits [2:0] rom 0x 0202 b pll2 frequency translation registers unused r2 , bits [3:0] rom 0x 0203 b n2 , bits [7:0] rom 0x 0204 b unused m2, bits [3:0] rom 0x 0205 b d2a d2a , bits [7:0] rom 0x0206 b out2_0 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x0207 b out2_1 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x 0208 b d2b d2b , bits [7:0] rom 0x0209 b out2_2 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x020a b out2_3 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x020b b out2_4 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x 020c b d2c d2c [7:0] rom 0x020d b out2_5 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom rev. 0 | page 58 of 88
data sheet AD9531 reg . addr . (hex) opt . name d7 d6 d5 d4 d3 d2 d1 d0 def . 0x020e b out2_6 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x020f b out2_7 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x 0210 b d2d d2d [7:0] rom 0x0211 b out2_8 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x0212 b out2_9 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x0213 b out2_10 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom 0x0214 b out2_11 unused logic mode, bits[2:0] polarity, bits[1:0] power - down rom pll3 registers 0x 0300 b pll3 general registers unused reserved xtal amp lifier reserved manual sync reserved power - down rom 0x 0301 b pll3 frequency translation registers unused 2b 2a reference scaling , bits [3:0] rom 0x 0302 b n3a , bits [7:0] rom 0x 0303 b r3b , bits [7:0] rom 0x 0304 b n3b , bits [7:0] rom 0x 0305 b out3_0 reserved d3a , bits [3:0] rom 0x 0306 b unused 3.3 v mode reserved invert power - down rom 0x 0307 b out3_1 reserved d3b , bits [3:0] rom 0x 0308 b unused logic mode , bits [3:0] polarity , bits [1:0] power - down rom rev. 0 | page 59 of 88
AD9531 data sheet register map detail s control bit functions are active high and register address values are hexadecimal , unless otherwise noted . serial port control registers register 0 x 0000 to register 0 x 0005 table 53. serial port control register details address bit s bit name description 0x0000 d 7 unused unused. d 6 lsb first bit order for the spi port. 0 (default): most significant bit first and, for multibyte transfers, most significant byte first with autodecrement register addressing. 1: least significant bit first and, for multibyte transfers, least significant byte first with autoincrement register addressing. d 5 soft reset software initiated reset. this bit restores register contents to the current rom profile values. [ d 4: d 0] unused unused. 0x0004 [ d 7: d 5] unused unused. d 4 hardware reset software initiated hardware reset. this bit resets the internal device hardware without changing the current register contents. this bit does not autoclear; therefore, for proper device operation, first write a logic 1 then, a logic 0. [ d 3: d 2] unused unused. d 1 reduce spi strength alters the strength of the spi port control pins. the default value for this bit resides in the rom. 0: normal spi strength. 1: reduced spi strength. d 0 read buffer register read cycle target (spi or buffered register(s)) . 0 (default) : r ead cycles apply to the spi registers . 1: r ead cycles apply to the buffered registers . 0x 0005 [ d 7: d 1] unused unused. d 0 i /o update software initiated input/output update. this is an auto clearing bit. device identificatio n and rom profile registers register 0x 000a to register 0 x 000e register 0x000a to register 0x 000d are r ead - only. writing to register 0x 000e invokes a rom load sequence. table 54. device identification and rom profile register details address bit s bit name description 0x 000a [ d 7: d 0] device id [31:24] most significant byte of the device id. 0x000b [ d 7: d 0] device id [23:16] next byte of the device id. 0x000c [ d 7: d 0] device id [15:8] next byte of the device id. 0x000d [ d 7: d 0] device id [7:0] least significant byte of the device id. 0x 000e [ d 7: d 6] reserved reserved. [ d 5: d 0] rom profile reading this register provides the index value of the most recently loaded rom profile. writing to the register selects one of 64 possible rom profiles. the contents of this regi ster are initially set at power - up as described in the multifunction pins (ldet1/m1, ldet2/m2, ldet3/m3, lor/m4) section. note t hat writing to this register loads the specified rom profile , thereby updating the value of all registers identified by rom in the default column of the register map . the c ontents of a register with rom in the default column of the register map depend on the rom p rofile number identified by the bits in this register (see the rom profile data section). rev. 0 | page 60 of 88
data sheet AD9531 status registers register 0 x 0080 to register 0 x 0082 register 0x 0080 to register 0x 0082 are read - only. table 55. status register details address bit s bit name description 0x 0080 [ d 7: d 6] reserved reserved. d 5 pll2 calibration in progress this bit reflects the state of the pll2 calibration controller. logic 1 indicates that the pll2 internal vco calibration is in progress. d 4 pll1 calibration in progress this bit reflects the state of the pll1 calibration controller. logic 1 indicates that the pll1 internal vco calibration is in progress. d 3 r eserved reserved . d 2 pll3 lock detect this bit reflects the state of the lock detector for pll3. logic 1 indicates a lock condition for pll3. d 1 pll2 lock detect this bit reflects the state of the lock detector for pll2. logic 1 indicates a lock condition for pll2. d 0 pll1 lock detect this bit reflects the state of the lock detector for pll1. logic 1 indicates a lock condition for pll1. 0x0081 [d7:d4] unused unused. d3 ref3 lor logic 1 indicates a loss of reference condition for pll3. only the first of the two cascaded plls of pll3 provides the lor status. d2 ref2 lor logic 1 indicates a loss of reference condition for pll2. d1 ref1b lor logic 1 indicates a loss of reference condition for pll1 ref1_b. d0 ref1a lor logic 1 indicates a loss of reference condition for pll1 ref1_a. 0x0082 [d7:d4] unused unused. d3 reserved reserved. d2 pll1 freerun this bit indicates (logic 1) pll1 is in freerun mode . d1 pll1 holdover this bit indicates (logic 1) pll1 is in holdover mode. d0 pll1 active reference this bit indicates the currently active reference. logic 0 indicates ref1_a i s the currently active reference. logic 1 indicates ref1_b i s the currently active reference . ldet/lor control registers register 0x 0083 to register 0 x 0085 register 0x 0083 controls the three ldet x pins. register 0x 0084 controls the lor pin , where bits [ d 4: d 0] provide logical or indication of the various loss of refe rence detec tors at the lor pin. register 0x 0085 controls the out3_0 pin of pll3 , where bits [ d 4: d 0] provide logical or indication of the various loss of referenced detectors on the out3_0 pin. when register 0x 0085 , bits[ d 4: d 0] = 00000, the out3_0 pin functi ons normally (that is, as the output of pll3). table 56. ldet x /lor control register details address bit s bit name description 0x0083 [ d 7: d 6] reserved reserved. d 5 ldet3 3.3 v mode 0: ldet3/m3 pin, 1.8 v mode. 1: ldet3/m3 pin, 3.3 v mode. d 4 ldet3 invert 0: ldet3/m3 pin normal (active high logic). 1: ldet3/m3 pin inverted (active low logic). d 3 ldet2 3.3 v mode 0: ldet2/m2 pin, 1.8 v mode. 1: ldet2/m2 pin , 3.3 v mode . d 2 ldet2 invert 0: ldet2/m2 pin normal (active high logic) . 1: ldet2/m2 pin inverted (active low logic). d 1 ldet1 3.3 v mode 0: ldet1/m1 pin, 1.8 v mode. 1: ldet1/m1 pin, 3.3 v mode. d 0 ldet1 invert 0: ldet1/m1 pin normal (active high logic). 1: ldet1/m1 pin inverted (active low logic). 0x 0084 d 7 reserved reserved. d 6 3.3 v mode 0: lor/m4 pin, 1.8 v mode. 1: lor/m4 pin, 3.3 v mode. d 5 invert 0: lor/m4 pin normal (active high logic). 1: lor/m4 pin inverted (active low logic). rev. 0 | page 61 of 88
AD9531 data sheet address bit s bit name description d 4 ref3 lor 0: d isallow s loss of reference indication on the lor/m4 pin by pll3 . 1: allows loss of reference indication on the lor/m4 pin by pll3. d 3 ref2 lor 0: d isallow s loss of reference indication on the lor/m4 pin by pll2 . 1: allows loss of reference indication on the lor/m4 pin by pll2. d 2 active ref1 lor 0: d isallow s loss of reference indication on the lor/m4 pin by the active reference of pll1 . 1: allows loss of reference indication on the lor/m4 pin by the active reference (ref1 _ a or ref1 _ b) of pll1. d 1 ref1b lor 0: d isallow s loss of reference indication on the lor/m4 pin by ref1_b of pll1 . 1: allows loss of reference indication on the lor/m4 pin by ref1_b of pll1. d 0 ref1a lor 0: d isallow s loss of reference indication on the lor/m4 pin by ref1_a of pll1 . 1: allows loss of reference indication on the lor/m4 pin by ref1_a of pll1. 0x 0085 d 7 reserved reserved. d 6 3.3 v mode this bit controls the output drive voltage of out3_0 when any bit of register 0x 0085 , bits [ d 4: d 0] is logic 1. in this case, out3_0 is a static logic output indicating lor status per t he drive voltage specified at this bit location (the drive voltage specified by this bit overrides register 0x0306, bit d 3 ). 0: out3_0 pin = 1.8 v mode lor indication. 1: out3_0 pin = 3.3 v mode lor indication. d 5 invert this bit controls the logical sense of ou t3_0 when any bit of register 0x 0085 , bits [ d 4: d 0] is logic 1 . in this case, out3_0 is a static logic output indicating lor status with the logical sense specified at this bit location (the logical sense specified by this bit overrides register 0x0306, bit d 1 ). 0: out3_0 pin normal (activ e high logic). 1: out3_0 pin inverted (active low logic) . d 4 ref3 lor 0: d isallow s loss of reference indication on the out3_0 pin by pll3 . 1: allows loss of reference indication on the out3_0 pin by pll3. d 3 ref2 lor 0: d isallow s loss of reference indication on the out3_0 pin by pll2 . 1: allows loss of reference indication on the out3_0 pin by pll2. d 2 active ref1 lor 0: d isallow s loss of reference indication on the out3_0 pin by the active reference of pll1 . 1: allows loss of reference indication on the out3_0 pin by active reference of pll1. d 1 ref1b lor 0: disallows loss of reference indication on the out3_0 pin by ref1_b of pll1 . 1: allows loss of reference indication on the out3_0 pin by ref1_b of pll1. d 0 ref1a lor 0: disallows loss of reference indication on the out3_0 pin by ref1_a of pll1 . 1: allows loss of reference indication on the out3_0 pin by ref1_a of pll1. pll1 registers pll1 general registers register 0 x 0100 to register 0 x 0103 table 57. pll1 general register details address bit s bit name description 0x0100 [ d 7: d 4] unused unused. d 3 reserved reserved. d 2 manual sync write logic 1 to this bit to arm the distribution synchronization circuit , then write logic 0 to cause the distribution channel dividers to synchronize (synchronization occurs on the falling edge of this bit). d 1 manual calibrate l ogic 1 causes the vco calibration sequence to execute for pll1. for robustness, write to this bit in three operatio ns: logic 0, logic 1, then logic 0 with an input/output update following each operation . d 0 power - down logic 1 causes a full power - down of pll1. 0x0101 d7 enable m1 during vco calibration 0: normal operation (default). the m1 divider is in a reset state during calibration to ensure a defined set of initial conditions at power - up or following a device reset. 1: causes the m1 divider to remain active during pll1 vco calibration. allows the user to observe the calibration process at the clock outputs of pll1. rev. 0 | page 62 of 88
data sheet AD9531 address bit s bit name description [d6:d5] fixed delay [1:0] these bits select a particular output distribution group when using the fixed delay function (see the pll1 loop 4 configuration section). 00: disables the fixed delay function. 01: selects out1_0x (group 1a outputs) as the fixed delay feedback source. 10: selects out1_4x (group 1b outputs) as the fixed delay feedback source. 11: selects out1_8x (group 1c outputs) as the fixed delay feedback source. [d4:d2] 3.3 v charge pump current [2:0] these bits establish the charge pump current for the 3.3 v charge pump of pll1 (used for controlling an external vcxo). 000: 625 a. 001: 1250 a. 010: 1875 a. 011: 2500 a. 100: 3125 a. 101: 3750 a. 110: 4375 a. 111: 5000 a. [d1:d0] external oscillator (vcxo) mode [1:0] these bits determine the functionality of the rfin_1p/rfin_1n pins when using an external loop configuration (see the pll1 loop configurations section ). 00: disables the external vcxo function. 01: single - ended input (rfin_1p). 10: single - ended input (rfin_1n). 11: differential input. 0x0102 d7 freerun logic 1 forces pll1 into freerun mode, but only if an external loop configuration is in effect. otherwise, logic 1 forces pll1 into holdover mode. d6 holdover logic 1 forces pll1 into holdover mode. d5 enable reference select 0: disables the functionality of the reference select bit. 1: enables the functionality of the reference select bit. d4 reference select this bit is ineffective when register 0x0102, bit d 5 = 0. 0: forces ref1_a to be the active reference for pll1. 1: forces ref1_b to be the active reference for pll1. d3 w ide bandwidth mode see the pll1 loop 2 wide bandwidth configuration section for details. 0: disables the wide bandwidth mode. 1: enables the wide bandwidth mode. d2 freerun vs. holdover logic 1 allows automatic transition to freerun mode instead of holdover mode. this transition is only effective when the enable auto hold bit is set and an external loop configuration is in effect. d1 enable autohold logic 1 activates the control logic that allows automatic transition to holdover mode when conditions warrant this transition. d0 enable autoswitch logic 1 activates the control logic that allows automatic switching to an alternate reference upon lor indication of the active reference. 0x0103 d7 vco calibration reset 0: normal operation (default) . 1: resets the pll1 vco calibration circuitry. this is a fail - safe control bit. normally, a reset of the calibration circuitry automatically occurs at the start of calibration. [d6:d5] ref1b input mode [1:0] these bits set the configuration of the ref1_b input reference. 00: differential input (ref1_bp/ref1_bn inputs active). 01: 3.3 v cmos single - ended (ref1_bp active, ref1_bn disabled). 10: not applicable. 11: 2.5 v cmos single - ended (ref1_bp active, ref1_bn disabled). d4 ref1b power - down logic 1 powers down the ref1_bp/ref1_bn inputs. d3 reserved reserved. rev. 0 | page 63 of 88
AD9531 data sheet address bit s bit name description [d2:d1] ref1a input mode [1:0] these bits set the configuration of the ref1_a input reference. 00: differential input (ref1_ap/ref1_an inputs active). 01: 3.3 v cmos single - ended (ref1_ap active, ref1_an disabled). 10: not applicable. 11: 2.5 v cmos single - ended (ref1_ap active, ref1_an disabled). d0 ref1a power - down logic 1 powers down the ref1_ap/ref1_an inputs. pll1 frequency translation registers register 0 x 0104 to register 0 x 010f table 58. pll1 frequency translation register details address bit s bit name description 0x 0104 [ d 7: d 0] r1 [7:0] r1 divider bit d 7 to bit d 0 (lsb). see register 0x 0105 , bits [ d 3: d 0] for details. 0x 0105 [ d 7: d 4] unused unused. [ d 3: d 0] r1 [11:8] r1 divider bit d 11 (msb) to bit d 8. the value of r1 , bits [ d 11: d 0] results in the following behavior: 0: multiplies the input frequency by a factor of 2. 1 to 3: passes the input frequency unaltered (r1 divider bypass). 4 to 4095: divides the input frequency by this value. 0x 0106 [ d 7: d 0] n1a [7:0] n1a bit d 7 (msb) to bit d 0 (lsb). the value of n1a [7:0] results in the following behavior , depending on the operating mode (integer - n or fractional - n): for integer - n mode, 0 to 14: not applicable. 15 to 255: divide by this value. for fractional - n mode, 0 to 79: not applicable. 80 to 255: divide by this value. 0x 0107 [ d 7: d 0] n1a fraction [7:0] n1a fraction bit d 7 to bit d 0 (lsb). see register 0x 0109 , bits [ d 3: d 0] for details. 0x 0108 [ d 7: d 0] n1a fraction [15:8] n1a fraction bit d 15 to bit d 8. see register 0x 0109 , bits [ d 3: d 0] for details. 0x 0109 [ d 7: d 4] reserved reserved. [ d 3: d 0] n1a fraction [19:16] n1a fraction bit d 19 (msb) to bit d 16. the value of n1a fraction [19:0] results in the following behavior: 0: enables integer mode (disables the - modulator). 1 to 1048574: enables fractional - n mode ( - modulator active). 0x 010a [ d 7: d 0] n1a modulus [7:0] n1a modulus bit d 7 to bit d 0 (lsb). see register 0x 010c , bits [ d 3: d 0] for details. 0x 010b [ d 7: d 0] n1a modulus [15:8] n1a modulus bit d 8 to bit d 15. see register 0x 010c , bits [ d 3: d 0] for details. 0x 010c [ d 7: d 4] reserved reserved. [ d 3: d 0] n1a modulus [19:16] n1a modulus bit d 19 (msb) to bit d 16. n1a modulus [19:0] must be greater than n1a f raction (1,048,575 maximum ). 0x 010d [ d 7: d 0] n1b [7:0] n1b bit d 7 to bit d 0 (lsb). see register 0x 010e , bits [ d 3: d 0] for details. 0x 010e [ d 7: d 4] unused unused. [ d 3: d 0] n1b [11:8] n1b bit d 11 (msb) to bit d 8. the value of n1b [11:0] results in the following behavior: 0 to 1: disallows the loop 2 configuration and bypasses the n1b divider. 2 to 3: undefined. 4 to 4095: divides the by this value. the loop 4 configuration bypasses the n1b divider regardless of the value of n1b [11:0]. 0x 010f [ d 7: d 4] unused unused. [ d 3: d 0] m1 [3:0] m1 bit d 3 (msb) to bit d 0. the value of the m1 [3:0] bits results in the following behavior: 0 to 2: disable. 3 to 11: divide by this value. 12 to 14 : disable s vco calibration after changing the value of m1. 15: m1 divider reset state. if the user intends to change the m1 divider without performing a subsequent pll1 vco calibration, then program this value (followed by an input/output update ) before programming the new m1 divider value (followed by an input/output update ). an input/output update is writing register 0x0005 , bit d 0 = 1. the procedure given here is unnecessary if the user performs a pll1 . rev. 0 | page 64 of 88
data sheet AD9531 registers for pll1 group 1a outputs, out1_0 x to out1_3 x register 0 x 0110 to register 0x0114 table 59. pll1 group 1a outputs register details address bit s bit name description 0x 0110 [ d 7: d 0] d1a [7:0] d1a divider bit d 7 (msb) to bit d 0 (lsb). the d ivide factor is the value of d1a [7:0] + 1. d1a powers down when all four of the associated output drivers power down , whether via the power - down bit or via the logic mode bits. 0x 0111 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] these bits c onfigure the out1_0 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out1_0p active, out1_0n active. 101: 1.8 v cmos, out1_0p active, out1_0n disabled. 110: 1.8 v cmos, out1_0p disabled, out1_0n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out1_0 x polarity as follows (applies to cmos only) : 00: out1_0p normal, out1_0n inverted. 01: out1_0p normal, out1_0n normal. 10: out1_0p inverted, out1_0n inverted. 11: out1_0p inverted, out1_0n normal. d 0 power - down 0: out1_0 x driver active. 1: out1_0 x driver powered down. 0x 0112 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out1_1 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out1_1p active, out1_1n active. 101: 1.8 v cmos, out1_1p active, out1_1n disabled. 110: 1.8 v cmos, out1_1p disabled, out1_1n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out1_1 x polarity as follows (applies to cmos only) : 00: out1_1p normal, out1_1n invert ed. 01: out1_1p normal, out1_1n normal . 10: out1_1p invert ed , out1_1n invert ed. 11: out1_1p invert ed , out1_1n normal . d 0 power - down 0: out1_1 x driver active . 1: out1_1 x driver power ed down . 0x 0113 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out1_2 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out1_2p active, out1_2n active. 101: 1.8 v cmos, out1_2p active, out1_2n disabled. 110: 1.8 v cmos, out1_2p disabled, out1_2n active. 111: undefined. rev. 0 | page 65 of 88
AD9531 data sheet address bit s bit name description [ d 2: d 1] polarity [1:0] configure out1_2 x polarity as follows (applies to cmos only) : 00: out1_2p normal, out1_2n inverted. 01: out1_2p normal, out1_2n normal. 10: out1_2p inverted, out1_2n inverted. 11: out1_2p inverted, out1_2n normal. d 0 power - down 0: out1_2 x driver active . 1: out1_2x driver powered down. 0x 0114 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out1_3 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out1_3p active, out1_3n active. 101: 1.8 v cmos, out1_3p active, out1_3n disabled. 110: 1.8 v cmos, out1_3p disabled, out1_3n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out1_3 x polarity as follows (applies to cmos only) : 00: out1_3p normal, out1_3n inverted. 01: out1_3p normal, out1_3n normal. 10: out1_3p inverted, out1_3n inverted. 11: out1_3p inverted, out1_3n normal. d 0 power - down 0: out1_3 x driver active . 1: out1_3x driver powered down. registers for pll1 group 1b outputs, out1_4 x to out1_7 x register 0 x 0115 to register 0 x 0119 table 60. pll1 group 1b outputs register details address bit s bit name description 0x 0115 [ d 7: d 0] d1b [7:0] d1b divider bit d 7 (msb) to bit d 0 (lsb). the d ivide factor is the value of d1b [7:0] + 1. d1b powers down when all four of the associated output drivers power down , whether via the power - down bit or via the logic mode bits. 0x 0116 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out1_4 x output driver as follows: 000: disabled. 001: hstl . 010: undefined. 011: undefined. 100: 1.8 v cmos, out1_4p active, out1_4n active . 101: 1.8 v cmos, out1_4p active, out1_4n disable d. 110: 1.8 v cmos, out1_4p disable d , out1_4n active . 111: undefined. [ d 2: d 1] polarity [1:0] configure out1_4 x polarity as follows (applies to cmos only): 00: out1_4p normal, out1_4n inverted. 01: out1_4p normal, out1_4n normal. 10: out1_4p inverted, out1_4n inverted. 11: out1_4p inverted, out1_4n normal. d 0 power - down 0: out1_4x driver active. 1: out1_4x driver powered down. rev. 0 | page 66 of 88
data sheet AD9531 address bit s bit name description 0x 0117 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure o ut1_5 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out1_5p active, out1_5n active. 101: 1.8 v cmos, out1_5p active, out1_5n disabled. 110: 1.8 v cmos, out1_5p disabled, out1_5n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out1_5 x polarity as follows (applies to cmos only) : 00: out1_5p normal, out1_5n inverted. 01: out1_5p normal, out1_5n normal. 10: out1_5p inverted, out1_5n inverted. 11: out1_5p inverted, out1_5n normal. d 0 power - down 0: out1_5 x driver active . 1: out1_5x driver powered down. 0x 0118 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure o ut1_6 output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out1_6p active, out1_6n active. 101: 1.8 v cmos, out1_6p active, out1_6n disabled. 110: 1.8 v cmos, out1_6p disabled, out1_6n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out1_6 x polarity as follows (applies to cmos only): 00: out1_6p normal, out1_6n inverted. 01: out1_6p normal, out1_6n normal. 10: out1_6p inverted, out1_6n inverted. 11: out1_6p inverted, out1_6n normal. d 0 power - down 0: out1_6x driver active. 1: out1_6x driver powered down. 0x 0119 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out1_7 x output driver as follow s: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out1_7p active, out1_7n active. 101: 1.8 v cmos, out1_7p active, out1_7n disabled. 110: 1.8 v cmos, out1_7p disabled, out1_7n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out1_7 x polarity as follows (applies to cmos only) : 00: out1_7p normal, out1_7n inverted. 01: out1_7p normal, out1_7n normal. 10: out1_7p inverted, out1_7n inverted. 11: out1_7p inverted, out1_7n normal. d 0 power - down 0: out1_7x driver active. 1: out1_7x driver powered down. rev. 0 | page 67 of 88
AD9531 data sheet registers for pll1 group 1c outputs, out1_8 x to out1_9 x register 0 x 011a to register 0 x 011c table 61. pll1 group 1c outputs address bit s bit name description 0x 011a [ d 7: d 0] d1c [7:0] d1c divider bit d 7 (msb) to bit d 0 (lsb). the d ivide factor is the value of d1c [7:0] + 1. d1c powers down when all four of the associated output drivers power down , whether via the power - down bit or via the logic mode bits. 0x 011b [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure out1_8 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out1_8p active, out1_8n active. 101: 1.8 v cmos, out1_8p active, out1_8n disabled. 110: 1.8 v cmos, out1_8p disabled, out1_8n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out1_8 polarity (applies to cmos, only) as follows: 00: out1_8p normal, out1_8n inverted. 01: out1_8p normal, out1_8n normal. 10: out1_8p inverted, out1_8n inverted. 11: out1_8p inverted, out1_8n normal. d 0 power - down 0: out1_8 x driver active . 1: out1_8x driver powered down. 0x 011c [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out1_9 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out1_9p active, out1_9n active. 101: 1.8 v cmos, out1_9p active, out1_9n disabled. 110: 1.8 v cmos, out1_9p disabled, out1_9n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out1_9 x polarity as follows (applies to cmos only) : 00: out1_9p normal, out1_9n inverted. 01: out1_9p normal, out1_9n normal. 10: out1_9p inverted, out1_9n inverted. 11: out1_9p inverted, out1_9n normal. d 0 power - down 0: out1_9 x driver active . 1: out1_9x driver powered down. rev. 0 | page 68 of 88
data sheet AD9531 pll2 registers pll2 general registers register 0x0200 register 0x0201 table 62. pll2 general register details address bit s bit name description 0x0200 [ d 7: d 6] unused unused. d 5 reserved reserved. d 4 xtal amp lifier 0: c onfigure s ref_2p/ ref_2 n as a differential clock input pair . 1: configures ref_2p/ ref_2n as a crystal resonator input. ref_2p/ ref_2n is the amplifier input/ output, respectively . d 3 reserved reserved. d 2 manual sync write logic 1 to arm the distribution synchronization circuit, then write logic 0 to cause the distribution channel dividers to synchronize (synchronization occurs on the falling edge of this bit). d 1 manual calibrate logic 1 causes the vco calibration sequence to execute for pll2. for robustness, write to this bit as three operations: logic 0, logic 1, then logic 0. d 0 p ower - down logic 1 causes a full power - down of pll2. 0x 0201 [ d 7: d 4] unused unused. d 3 manual charge pump current 0: automatic charge pump current control (recommended) . 1: enable manual charge pump current control via register 0x0201, bits[ d 2: d 0]. [ d 2: d 0] charge pump current [2:0] charge pump current control bits . these bits are ineffective when register 0x0201, bit d 3 = 0. 000: 125 a. 001: 250 a. 010: 375 a. 011: 500 a. 100: 625 a. 101: 750 a. 110: 875 a. 111: 1000 a. pll2 frequency translation registers register 0 x 0202 to register 0 x 0204 table 63. pll2 frequency translation register details address bit s bit name description 0x 0202 [ d 7: d 4] unused unused. [ d 3: d 0] r2 [3:0] r2 divider bit d 3 (msb) to bit d 0. the value of r2 [3:0] results in the following behavior: 0: divides the input frequency by 16. 1 to 15: divides the input frequency by this value. 0x 0203 [ d 7: d 0] n2 [7:0] n2 bit d 7 (msb) to bit d 0 (lsb). the value of n2 [7:0] results in the following behavior: 0 to 19: not applicable. 20 to 255: divides by this value. 0x 0204 [ d 7: d 4] unused unused. [ d 3: d 0] m2 [3:0] m2 bit d 3 (msb) to bit d 0. the value of the m2 [3:0] bits results in the following behavior: 0 to 2: disabled. 3 to 11: divides by this value. 12 to 14: disable. 15: m2 divider reset state. if the user intends to change the m2 divider without performing a subsequent pll2 vco calibration, then program this value (followed by an input/output update ) before programming the a new m2 divider value (followed by an input/output update ). an input/output update is writing register 0x0005 , bit d 0 = 1. the procedure given h ere is unnecessary if the user performs a pll2 vco calibration after changing the value of m2. rev. 0 | page 69 of 88
AD9531 data sheet registers for pll2 group 2a outputs, out2_0 x to out2_1 x register 0 x 0205 to register 0 x 0207 table 64. pll2 group 2a outputs register details address bit s bit name description 0x 0205 [ d 7: d 0] d2a [7:0] d2a divider bit d 7 (msb) to bit d 0 (lsb). the d ivide factor is the value of d2a [7:0] + 1. d2a powers down when all four of the associated output drivers power down , whether via the power - down bit or via the logic mode bits. 0x 0206 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out2_0 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out2_0p active, out2_0n active. 101: 1.8 v cmos, out2_0p active, out2_0n disabled. 110: 1.8 v cmos, out2_0p disabled, out2_0n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out2_0 x polarity as follows (applies to cmos only) : 00: out2_0p normal, out2_0n inverted. 01: out2_0p normal, out2_0n normal. 01: out2_0p normal, out2_0n normal. 11: out2_0p inverted, out2_0n normal. 0 power - down 0: out2_0 x driver active . 1: out2_0x driver powered down. 0x 0207 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out2_1 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out2_1p active, out2_1n active. 101: 1.8 v cmos, out2_1p active, out2_1n disabled. 110: 1.8 v cmos, out2_1p disabled, out2_1n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out2_1x polarity as follows (applies to cmos only) : 00: out2_1p normal, out2_1n inverted. 01: out2_1p normal, out2_1n normal. 10: out2_1p inverted, out2_1n inverted. 11: out2_1p inverted, out2_1n normal. d 0 power - down 0: out2_1 x driver active . 1: out2_1x driver powered down. rev. 0 | page 70 of 88
data sheet AD9531 registers for pll2 group 2b outputs, out2_2 x to out2_4 x register 0 x 0208 to register 0 x 020b table 65. pll2 group 2b outputs register details address bit s bit name description 0x 0208 [ d 7: d 0] d2b [7:0] d2b divider bit d 7 (msb) to bit d 0 (lsb). the d ivide factor is the value of d2b [7:0] + 1. d2b powers down when all four of the associated output drive rs p ower down whether via the power - down bit or via the logic mode bits. 0x 0209 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure o ut2_2x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out2_2p active, out2_2n active. 101: 1.8 v cmos, out2_2p active, out2_2n disabled. 110: 1.8 v cmos, out2_2p disabled, out2_2n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out2_2 x polarity as follows (applies to cmos only): 00: out2_2p normal, out2_2n inverted. 01: out2_2p normal, out2_2n normal. 10: out2_2p inverted, out2_2n inverted. 11: out2_2p inverted, out2_2n normal. d 0 power - down 0: out2_2x driver active. 1: out2_2x driver powered down. 0x 020a [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out2_3 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out2_3p active, out2_3n active. 101: 1.8 v cmos, out2_3p active, out2_3n disabled. 110: 1.8 v cmos, out2_3p disabled, out2_3n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out2_3 x polarity as follows (applies to cmos only) : 00: out2_3p normal, out2_3n inverted. 01: out2_3p normal, out2_3n normal. 10: out2_3p inverted, out2_3n inverted. 11: out2_3p inverted, out2_3n normal. d 0 power - down 0: out2_3x driver active. 1: out2_3x driver powered down. 0x 020b [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the o ut2_4 x output driver as follows: 000: disabled. 001: hstl . 010: undefined . 011: undefined . 100: 1.8 v cmos, out2_4p active, out2_4n active . 101: 1.8 v cmos, out2_4p active, out2_4n disable d. 110: 1.8 v cmos, out2_4p disabled , out2_4n active . 111: undefined . rev. 0 | page 71 of 88
AD9531 data sheet address bit s bit name description [ d 2: d 1] polarity [1:0] configure out2_4 x polarity as follows (applies to cmos only) : 00: out2_4p normal, out2_4n inverted. 01: out2_4p normal, out2_4n normal. 10: out2_4p inverted, out2_4n inverted. 11: out2_4p inverted, out2_4n normal. d 0 power - down 0: out2_4x driver active. 1: out2_4x driver powered down. registers for pll2 group 2c outputs , out2_5 x to out2_7 x register 0 x020c to register 0x 020f table 66. pll2 group 2c outputs register details address bit s bit name description 0x 020c [ d 7: d 0] d2c [7:0] d2c d ivider bit d 7 (msb) to bit d 0 (lsb). the d ivide factor is the value of d2c [7:0] + 1. d2c powers down when all four of the associated output drivers power down , whether via the power - down bit or via the logic mode bits. 0x 020d [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out2_5 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out2_5p active, out2_5n active. 101: 1.8 v cmos, out2_5p active, out2_5n disabled. 110: 1.8 v cmos, out2_5p disabled, out2_5n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out2_5 x polarity as follows (applies to cmos only) : 00: out2_5p normal, out2_5n inverted . 01: out2_5p normal, out2_5n normal . 10: out2_5p inverted, out2_5n inverted . 11: out2_5p inverted, out2_5n normal . d 0 power - down 0: out2_5 x driver active . 1: out2_5x driver powered down. 0x 020e [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out2_6 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out2_6p active, out2_6n active. 101: 1.8 v cmos, out2_6p active, out2_6n disabled. 110: 1.8 v cmos, out2_6p disabled, out2_6n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out2_6 x polarity as follows (applies to cmos only) : 00: out2_6p normal, out2_6n inverted. 01: out2_6p normal, out2_6n normal. 10: out2_6p inverted, out2_6n inverted. 11: out2_6p inverted, out2_6n normal. d 0 power - down 0: out2_6x driver active. 1: out2_6x driver powered down. rev. 0 | page 72 of 88
data sheet AD9531 address bit s bit name description 0x 020f [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the o ut2_7x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out2_7p active, out2_7n active. 101: 1.8 v cmos, out2_7p active, out2_7n disabled. 110: 1.8 v cmos, out2_7p disabled, out2_7n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out2_7 x polarity as follows (applies to cmos only) : 00: out2_7p normal, out2_7n inverted. 01: out2_7p normal, out2_7n normal. 10: out2_7p inverted, out2_7n inverted. 11: out2_7p inverted, out2_7n normal. d 0 power - down 0: out2_7x driver active. 1: out2_7x driver powered down. registers for pll2 group 2d outputs, out2_8 x to out2_11 x register 0 x 0210 to register 0 x 0214 table 67. pll2 group 2d outputs register details address bit s bit name description 0x 0210 [ d 7: d 0] d2d [7:0] d2d divider bit d 7 (msb) to bit d 0 (lsb). the d ivide factor is the value of d2d [7:0] + 1. d2d powers down when all four of the associated output drivers power down , whether via the power - down bit or via the logic mode bits. 0x 0211 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out2_8 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out2_8p active, out2_8n active. 101: 1.8 v cmos, out2_8p active, out2_8n disabled. 110: 1.8 v cmos, out2_8p disabled, out2_8n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out2_8 x polarity as follows (applies to cmos only) : 00: out2_8p normal, out2_8n inverted. 01: out2_8p normal, out2_8n normal. 10: out2_8p inverted, out2_8n inverted. 11: out2_8p inverted, out2_8n normal. d 0 power - down 0: out2_8 x driver active . 1: out2_8x driver powered down. 0x 0212 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure out2_9 output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out2_9p active, out2_9n active . 101: 1.8 v cmos, out2_9p active, out2_9n disabled. 110: 1.8 v cmos, out2_9p disabled , out2_9n active . 111: undefined . rev. 0 | page 73 of 88
AD9531 data sheet address bit s bit name description [ d 2: d 1] polarity [1:0] configure out2_9 x polarity as follows (applies to cmos only) : 00: out2_9p normal, out2_9n inverted . 01: out2_9p normal, out2_9n normal . 10: out2_9p inverted , out2_9n inverted. 11: out2_9p inverted , out2_9n normal . d 0 power - down 0: out2_9 x driver active . 1: out2_9x driver powered down. 0x 0213 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the out2_10 x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out2_10p active, out2_10n active. 101: 1.8 v cmos, out2_10p active, out2_10n disable. 110: 1.8 v cmos, out2_10p disable, out2_10n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out2_10 x polarity as follows (applies to cmos only) : 00: out2_10p normal, out2_10n inverted. 01: out2_10p normal, out2_10n normal. 10: out2_10p inverted, out2_10n inverted. 11: out2_10p inverted, out2_10n normal. d 0 power - down 0: out2_10x driver active. 1: out2_10x driver powered down. 0x 0214 [ d 7: d 6] unused unused. [ d 5: d 3] logic mode [2:0] configure the ou t2_11x output driver as follows: 000: disabled. 001: hstl. 010: undefined. 011: undefined. 100: 1.8 v cmos, out2_11p active, out2_11n active. 101: 1.8 v cmos, out2_11p active, out2_11n disabled. 110: 1.8 v cmos, out2_11p disabled, out2_11n active. 111: undefined. [ d 2: d 1] polarity [1:0] configure out2_11 x polarity as follows (applies to cmos only) : 00: out2_11p normal, out2_11n inverted. 01: out2_11p normal, out2_11n normal. 10: out2_11p inverted, out2_11n inverted. 11: out2_11p inverted, out2_11n normal. d 0 power - down 0: out2_11x driver active. 1: out2_11x driver powered down. rev. 0 | page 74 of 88
data sheet AD9531 pll3 registers pll3 general register register 0 x 0300 table 68. pll3 general register details address bit s bit name description 0x0300 [ d 7: d 6] unused unused. d 5 reserved reserved. d 4 xtal amp lifier 0: configures ref_3p/ ref_3 n as a differential clock input pair . 1: configures ref_3p/ref_3n as a crystal resonator input. ref_3p/ref_3n is amplifier input/output, respectively. d 3 reserved reserved. d 2 manual sync write logic 1 to arm the distribution synchronization circuit, then write logic 0 to cause the distribution channel dividers to synchronize (synchronization occurs on the falling edge of this bit). d 1 reserved reserved. d 0 power - down logic 1 causes a full power - down of pll3. pll3 frequency translation registers register 0 x 0301 to register 0 x 0304 table 69. pll3 frequency translation register details address bit s bit name description 0x 0301 [ d 7: d 6] unused unused. d 5 2b logic 1 enables the 2 vco frequency multiplier of pll3b. d 4 2a logic 1 enables the 2 vco frequency multiplier of pll3a. [ d 3: d 0] reference scaling [3:0] reference scaling, bit d 3 (msb) to bit d 0 (lsb). the value of the reference scaling bits results in the following behavior: 0: disables reference input section. 1: passes the input frequency unaltered (bypasses r3a). 2: divides the input frequency by 1.5. 3: divides the input frequency by 2. 4: divides the input frequency by 3. 5: divides the input frequency by 4. 6: divides the input frequency by 6. 7: divides the input frequency by 8. 8 to 15: multiplies the input frequency by a factor of 2. 0x 0302 [ d 7: d 0] n3a [7:0] n3a bit d 7 (msb) to bit d 0 (lsb). the value of n3a [7:0] re sults in the following behavior (a void values not included in the following ranges ): 0: bypasses pll3a. 8 to 80: divides by this value when 2a = 0. 15 to 161: divides by this value when 2a = 1. 0x 0303 [ d 7: d 0] r3b [7:0] r3b bit d 7 (msb) to bit d 0 (lsb). the value of r3b [7:0] re sults in the following behavior (a void values not included in the following ranges ): 0: bypasses r3b divider. 2 to 10: divides by this value when n3 = 0. 8 to 80: divides by this value when n3 0. 0x 0304 [ d 7: d 0] n3b [7:0] n3b bit d 7 (msb) to bit d 0 (lsb). the value of n3b [7:0] re sults in the following behavior (a void values not included in the following ranges ): 0: bypasses pll3b. 8 to 80: divides by this value when 2b = 0. 15 to 161: divides by this value when 2b = 1. rev. 0 | page 75 of 88
AD9531 data sheet pll3 out3_0 registers register 0 x 0305 to register 0 x 0306 table 70. pll3 out3_0 register det a i ls address bit s bit name description 0x 0305 [ d 7: d 4] reserved reserved. [ d 3: d 0] d3a [3:0] d3a divider , bit d 3 (msb) to bit d 0 (lsb). the actual channel divide value is twice the value indicated in this table, due to the fixed divide by 2 that follows d3a. d3a powers down when the out3_0 driver powers down. the value of d3a [3:0] results in the following behavior: 0: divides by 16. 1 to 15: divides by this value. 0x 0306 [ d 7: d 4] unused unused. d 3 3.3 v mode this bit is only effective when register 0x 0085 , bits [ d 4: d 0] = 00000. 0: 1.8 v cmos output driver. 1: 3.3 v cmos output driver. d 2 reserved reserved. d 1 invert 0: out3_0 normal logic output . 1: out3_0 inverted logic output. d 0 power - down this bit is only effe ctive when register 0x 0085 , bits [ d 4: d 0] = 00000. 0: out3_0 driver active. 1: out3_0 driver powered down. pll3 out3_1 x registers register 0 x 0307 to register 0 x 0308 table 71. pll out3_1 register details address bit s bit name description 0x 0307 [ d 7: d 4] reserved reserved. [ d 3: d 0] d3b [3:0] d3b divider bit d 3 (msb) to bit d 0 (lsb). the actual channel divide value is twice the value indicated in this table, due to the fixed divide by 2 that follows d3b. d3b powers down when the out3_1x driver powers down. the value of d3b [3:0] results in the following behavior: 0: divides by 16. 1 to 15: divides by this value. 0x 0308 d 7 unused unused. [ d 6: d 3] logic mode [3:0] configure out3_1 output driver as follows: 0000: disabled. 0001: hstl. 0010: lvds. 0011: undefined. 0100: 1.8 v cmos, out3_1p active, out3_1n active. 0101: 1.8 v cmos, out3_1p active, out3_1n disabled. 0110: 1.8 v cmos, out3_1p disabled, out3_1n active. 0111 to 1011: undefined. 1100: 3.3 v cmos, out3_1p active, out3_1n active. 1101: 3.3 v cmos, out3_1p active, out3_1n disabled. 1110: 3.3 v cmos, out3_1p disabled, out3_1n active. 1111: undefined. [ d 2: d 1] polarity [1:0] configure out3_1 polarity as follows (applies to cmos only) : 00: out3_1p normal, out3_1n inverted. 01: out3_1p normal, out3_1n normal. 10: out3_1p inverted, out3_1n inverted. 11: out3_1p inverted, out3_1n normal. d 0 power - down 0: out3_1 x driver active . 1: out3_1x driver powered down. rev. 0 | page 76 of 88
data sheet AD9531 rom profile data the tables in this section contain the rom contents organized in columns by the rom p rofile number (as defined by th e value contained in register 0x 000e , bits[ d 5: d 0]). the left most column of the table contains t he register a ddress. the rom p rofile contents app ear as 8 - bit hexadecim al values. a void loading reserved rom profiles. r eserved profile s are noted in table 72, table 73 , table 74 , and table 75. rom profile 0 to rom profile 15 table 72. rom contents for rom profile 0 to rom profile 15 register address rom profile number 0 1 2 3 4 5 6 1 5 status controls 0x0083 0x0a 0x2a 0x00 0x00 0x00 0x00 these profiles are all reserved 0x0084 0x41 0x41 0x01 0x01 0x01 0x01 0x0085 0x42 0x42 0x02 0x02 0x02 0x02 pll1 0x0100 0x02 0x00 0x02 0x00 0x02 0x00 these profiles are all reserved 0x0101 0x00 0x0d 0x00 0x0d 0x00 0x0d 0x0102 0x08 0x00 0x08 0x00 0x08 0x00 0x0103 0x00 0x22 0x00 0x22 0x00 0x22 0x0104 0x01 0x7d 0x01 0x7d 0x01 0x7d 0x0105 0x00 0x00 0x00 0x00 0x00 0x00 0x0106 0x1e 0x00 0x1e 0x00 0x1e 0x00 0x0107 0x00 0x00 0x00 0x00 0x00 0x00 0x0108 0x00 0x00 0x00 0x00 0x00 0x00 0x0109 0x00 0x00 0x00 0x00 0x00 0x00 0x010a 0x00 0x00 0x00 0x00 0x00 0x00 0x010b 0x00 0x00 0x00 0x00 0x00 0x00 0x010c 0x00 0x00 0x00 0x00 0x00 0x00 0x010d 0x00 0x00 0x00 0x08 0x00 0x00 0x010e 0x00 0x06 0x00 0x07 0x00 0x06 0x010f 0x03 0x00 0x03 0x00 0x03 0x00 0x0110 0x09 0x00 0x07 0x00 0x09 0x00 0x0111 0x08 0x08 0x08 0x08 0x08 0x08 0x0112 0x08 0x08 0x08 0x08 0x08 0x08 0x0113 0x08 0x08 0x08 0x08 0x08 0x08 0x0114 0x08 0x08 0x08 0x08 0x08 0x08 0x0115 0x09 0x00 0x07 0x00 0x09 0x00 0x0116 0x08 0x08 0x08 0x08 0x08 0x08 0x0117 0x08 0x08 0x08 0x08 0x08 0x08 0x0118 0x08 0x08 0x08 0x08 0x08 0x08 0x0119 0x08 0x08 0x08 0x08 0x08 0x08 0x011a 0x09 0x00 0x07 0x00 0x09 0x00 0x011b 0x08 0x08 0x08 0x08 0x08 0x08 0x011c 0x08 0x08 0x08 0x08 0x08 0x08 rev. 0 | page 77 of 88
AD9531 data sheet register address rom profile number 0 1 2 3 4 5 6 1 5 pll2 0x0200 0x02 0x02 0x02 0x02 0x02 0x02 these profiles are all reserved 0x0201 0x00 0x00 0x00 0x00 0x00 0x00 0x0202 0x01 0x01 0x01 0x01 0x01 0x01 0x0203 0x032 0x032 0x032 0x032 0x032 0x032 0x0204 0x04 0x04 0x04 0x04 0x04 0x04 0x0205 0x04 0x03 0x03 0x03 0x04 0x03 0x0206 0x08 0x08 0x08 0x08 0x08 0x08 0x0207 0x08 0x08 0x08 0x08 0x08 0x08 0x0208 0x03 0x04 0x03 0x03 0x03 0x04 0x0209 0x08 0x08 0x08 0x08 0x08 0x08 0x020a 0x08 0x08 0x08 0x08 0x08 0x08 0x020b 0x08 0x08 0x08 0x08 0x08 0x08 0x020c 0x04 0x04 0x03 0x03 0x04 0x04 0x020d 0x08 0x08 0x08 0x08 0x08 0x08 0x020e 0x08 0x08 0x08 0x08 0x08 0x08 0x020f 0x08 0x08 0x08 0x08 0x08 0x08 0x0210 0x04 0x04 0x03 0x03 0x04 0x04 0x0211 0x08 0x08 0x08 0x08 0x08 0x08 0x0212 0x08 0x08 0x08 0x08 0x08 0x08 0x0213 0x08 0x08 0x08 0x08 0x08 0x08 0x0214 0x08 0x08 0x08 0x08 0x08 0x08 pll3 0x0300 0x01 0x00 0x01 0x00 0x01 0x00 these profiles are all reserved 0x0301 0x00 0x01 0x00 0x01 0x00 0x01 0x0302 0x00 0x4b 0x00 0x4b 0x00 0x4b 0x0303 0x00 0x00 0x00 0x00 0x00 0x00 0x0304 0x00 0x00 0x00 0x00 0x00 0x00 0x0305 0x00 0x00 0x00 0x00 0x00 0x00 0x0306 0x00 0x01 0x00 0x01 0x00 0x01 0x0307 0x00 0x0f 0x00 0x0f 0x00 0x0f 0x0308 0x00 0x28 0x00 0x28 0x00 0x28 0x0309 0x00 0x00 0x00 0x00 0x00 0x00 0x030a 0x00 0x00 0x00 0x00 0x00 0x00 0x030b 0x00 0x00 0x00 0x00 0x00 0x00 0x030c 0x00 0x00 0x00 0x00 0x00 0x00 0x030d 0x00 0x00 0x00 0x00 0x00 0x00 0x030e 0x00 0x00 0x00 0x00 0x00 0x00 rom profile 16 to ro m profile 31 table 73. rom contents for rom profile 16 to rom profile 31 register address rom profile number 16 rom profile number 31 status controls 0x0083 these profiles are all reserved 0x0084 0x0085 rev. 0 | page 78 of 88
data sheet AD9531 register address rom profile number 16 rom profile number 31 pll1 0x0100 these profiles are all reserved 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 0x0108 0x0109 0x010a 0x010b 0x010c 0x010d 0x010e 0x010f 0x0110 0x0111 0x0112 0x0113 0x0114 0x0115 0x0116 0x0117 0x0118 0x0119 0x011a 0x011b 0x011c pll2 0x0200 these profiles are all reserved 0x0201 0x0202 0x0203 0x0204 0x0205 0x0206 0x0207 0x0208 0x0209 0x020a 0x020b 0x020c 0x020d 0x020e 0x020f 0x0210 0x0211 0x0212 0x0213 0x0214 rev. 0 | page 79 of 88
AD9531 data sheet register address rom profile number 16 rom profile number 31 pll3 0x0300 these profiles are all reserved 0x0301 0x0302 0x0303 0x0304 0x0305 0x0306 0x0307 0x0308 0x0309 0x030a 0x030b 0x030c 0x030d 0x030e rom profile 32 to ro m profile 47 table 74. rom contents for rom profile 32 to rom profile 47 register address rom profile number 32 rom profile number 47 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 status controls 0x0083 these profiles are all reserved 0x0084 0x0085 pll1 0x0100 these profiles are all reserved 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 0x0108 0x0109 0x010a 0x010b 0x010c 0x010d 0x010e 0x010f 0x0110 0x0111 0x0112 0x0113 0x0114 0x0115 0x0116 0x0117 0x0118 0x0119 rev. 0 | page 80 of 88
data sheet AD9531 register address rom profile number 32 rom profile number 47 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 0x011a 0x011b 0x011c pll2 0x0200 these profiles are all reserved 0x0201 0x0202 0x0203 0x0204 0x0205 0x0206 0x0207 0x0208 0x0209 0x020a 0x020b 0x020c 0x020d 0x020e 0x020f 0x0210 0x0211 0x0212 0x0213 0x0214 pll3 0x0300 these profiles are all reserved 0x0301 0x0302 0x0303 0x0304 0x0305 0x0306 0x0307 0x0308 0x0309 0x030a 0x030b 0x030c 0x030d 0x030e rev. 0 | page 81 of 88
AD9531 data sheet rom profile 48 to ro m profile 63 table 75. rom contents for rom profile 48 to rom profile 63 register address rom profile number 48 rom profile number 63 status controls 0x0083 these profiles are all reserved 0x0084 0x0085 pll1 0x0100 these profiles are all reserved 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 0x0108 0x0109 0x010a 0x010b 0x010c 0x010d 0x010e 0x010f 0x0110 0x0111 0x0112 0x0113 0x0114 0x0115 0x0116 0x0117 0x0118 0x0119 0x011a 0x011b 0x011c rev. 0 | page 82 of 88
data sheet AD9531 register address rom profile number 48 rom profile number 63 pll2 0x0200 these profiles are all reserved 0x0201 0x0202 0x0203 0x0204 0x0205 0x0206 0x0207 0x0208 0x0209 0x020a 0x020b 0x020c 0x020d 0x020e 0x020f 0x0210 0x0211 0x0212 0x0213 0x0214 pll3 0x0300 these profiles are all reserved 0x0301 0x0302 0x0303 0x0304 0x0305 0x0306 0x0307 0x0308 0x0309 0x030a 0x030b 0x030c 0x030d 0x030e rev. 0 | page 83 of 88
AD9531 data sheet thermal performance thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 76 . thermal parameters for the AD9531 88 - lead lfcsp package symbol thermal characteristic using a jedec51 - 7 plus jedec51 - 5 2s2p test board 1 value 2 unit ja junction -to - ambient thermal resistance, 0.0 m/s ec airflow per jedec jesd51 - 2 (still air) 18 c/w jma junction -to - amb ient thermal resistance, 1.0 m/sec airflow per jedec jesd51 - 6 (moving air) 16 c/w jma junction -to - ambient thermal resistance, 2.5 m/sec airflow per jedec jesd51 - 6 (moving air) 14 c/w jb junction -to - board thermal resistance, 1.0 m/sec airflow per jedec jesd51 - 8 (moving air) 9 c/w jc junction -to - case thermal resistance (die to heat sink) per mil - std 883, method 1012.1 1.0 c/w jt junction -to - top - of - package characterization paramet er, 0 m/sec airflow per jedec jesd51 - 2 (still air) 0.1 c/w 1 the exposed pad on the bottom of the package must be soldered to ground to achieve the specified thermal performance. 2 results are from simulations. the printed circuit board ( pcb ) is a jedec multilayer type. thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. the AD9531 is specified for a case temperature (t case ). to prevent exceeding t case , use an airflow source. use the followin g equation to determine the junction tempera ture on the application pcb: t j = t case + ( jt pd ) where: t j is the junction temperature (c). t case is the case temperature (c) measured by the customer at the top center of the package. jt is the value as indicated in table 76. pd is the power dissipation (see table 3 ). value s of ja are provided for package comparison and pcb design considerations. ja can be used for a first - order approx - imation of t j by the following equation : t j = t a + ( ja pd ) where t a is the ambient temperature (c). value s of jc are provided for package comparison and pcb design considerations when an external heat sink is required. value s of jb are provided for package comparison and pcb design considerations. rev. 0 | page 84 of 88
data sheet AD9531 applications informa tion interfacing to the m ultifunction pins figure 38 and figure 39 demonstrate using the mx pins with a 1.8 v cmos logic. for proper operation during a por event, the internal buffer requires a nominal 10 k? resistor to pull - up to 1.8 v ( logic 1) or pull - down to ground ( logic 0). after a por event ( with s1 in the norm position), the internal cmos driver force s the appropriate 1.8 v logic levels across the 10 k pull - up or pull - down resistor. por norm mx 1.8v s1 AD9531 1.8v cmos 10k? 1.8v 12973-037 figure 38 . using an mx pin with a 1.8 v cmos logic, pull - up connection por norm mx 1.8v s1 AD9531 1.8v cmos 10k? 12973-038 39 18 - figure 40 and figure 41 demonstrate using the mx pins with a 3.3 v cmos logic. for proper opera tion during a por event, the internal buffer requires a nominal 10 k? resistor to pull - up to 1.8 v ( logic 1) or pull - down to ground ( logic 0). after a por event (normal operation), the internal cmos driver force s the appropriate 3.3 v logic levels across t he 10 k? pull - up or pull - down resistor. note that interfacing to 3.3 v cmos requires programming the 3.3 v m ode bit to logic 1 for the associated pin function (ldetx or lor). por norm mx 1.8v s1 AD9531 3.3v cmos 10k? 1.8v 3.3v mode 12973-039 figure 40 . using an mx pin with a 3.3 v logic, pull - up configuration por norm mx 1.8v s1 AD9531 3.3v cmos 10k? 3.3v mode 12973-040 41 33 - figure 42 and figure 43 demonstrate using the mx pins with a 1.5 v cmos logic in a pull - down configuration. a resistive voltage divider is nece ssary to properly translate a logic 1 produced by the internal driver during normal operation from 1.8 v to 1.5 v. therefore, the ratio of the resistors is 5:1. note the external resistors have no impact on a logic 1 produced by the internal driver. the pr imary design constraint is the load current (i l ) that the driver must supply for a condition of logic 1. assuming the input of the external cmos gate exhibits high impedance, then all the load current flows through the 5r resistor, which must drop 1.5 v. t his implies 5r = 1.5 v/i l or r = 0.3 v/i l . therefore, choose a reasonable load current, such as 1 ma, for example. this load current yields r = 300 and 5r = 1.5 k. during a por event, the pull - down configuration provides the internal buffer with a 1.8 k? termination to ground , which the internal buffer i nterprets as logic 0. alternately, during normal operation, the internal 1.8 v driver delivers a 1.5 v logic 1 to the external cmos gate with 1 ma of load current. por norm mx 1.8v s1 AD9531 1.5v cmos 5r r 12973-041 figure 42 . u sing an mx pin with 1.5 v logic, pull - down configuration during a por event por norm mx 1.8v s1 AD9531 1.5v cmos 5r r 12973-042 43 15 - rev. 0 | page 85 of 88
AD9531 data sheet figure 44 and figure 45 demonstrate using the mx pins with a 1.5 v cmos logic in a pull - up configuration. a three resistor arrangement is necessary to satisfy two design criteria as follows : ? translate a 1.8 v logic 1 , produced by the internal driver , to 1.5 v for the external cmos gate during normal operation. ? provide the desired logic 1 pull - up to the internal buffer during a por event. the primary design constraint on the pull - up resistor (r u ) is the logic 0 load c urrent (i l ) it imposes on the internal driver during normal operation. assuming the external cmos gate exhibits high impedance, then r u = 1.8 v/i l . therefore, choose a reasonable load current, such as 1 ma, for example. this yields r u = 1.8 k? . por norm mx 1.8v s1 AD9531 1.5v 1.8v cmos 5r r u r 12973-043 figure 44 . using an mx pin with a 1.5 v logic, pull - up configuration during a por event 1.5v 1.8v cmos 5r r u r por norm mx 1.8v s1 AD9531 12973-044 45 15 - in the pull - down case, the ser ies and pull - down resistors must exhibit a 5:1 ratio to provide the desired 1.8 v to 1.5 v logic 1 translation between the internal driver and the external cmos gate during normal operation. therefore , the respective r and 5r label for the series and pull - down resistors. the design goal is to have at least 1.2 v (that is, 2/3 of 1.8 v) on the mx pin during a por event to constitute the desired logic 1 . r u , r , and 5r form a voltage divider. this divider sets up the following necessary design constraint: v 2 . 1 5 5 v 8 . 1 > + + + r r r r r u bcaus r u 1 v l t ao constraint simlifis to r l and ain cosn l 1 ma t rsult is r trfor coos a connint alu suc as r 1 tis imlis tat r interfacing to the r fin1 _x pins figure 46 is the recommended method for interfacing an external vcxo with a 3.3 v cmos single - ended output to the rfin 1_x pins. even though the v cxo has a single - ended output, it is best to configure the rfin1 _x input for differential input mode to minimize duty cycle distortion. this circuit works well as long as the stray pcb capacitance (c s ) is less than 10 pf and the vcxo frequency is in the ra nge of 120 mhz. the 0.1 f capacitor on the rfin1_n input provides a suitable ac ground reference for the two 5 pf capacitors, which serve as a voltage divider for the rising and falling signal edges delivered by the vcxo output. typically, the cmos driver s of most vcxos tend to have low output drive capability to minimize output switching noise and emi. ther e fore, choose small divider capacitor values to avoid excessive loading of the cmos output driver of the vcxo. rfin1_ p rfin1_n 1.8v n n 3.3v t olerant AD9531 0.1f 3pf 5pf c s vcxo 3.3v str a y pcb ca p aci t ance 5pf input ca p aci t ance manu f acturer: t aitien p/n: vteualjanf-122.88000 33 34 0.68v 12973-045 figure 46 . connecting an external 3.3 v cmos vcxo single - ended output to the rfin1_x pins rev. 0 | page 86 of 88
data sheet AD9531 driving ref2 or ref3 with 3.3 v cmos logic for applications with a 3.3 v cmos driver as the reference source, a single - ended to differential conversion is necessary , as shown in figure 47. AD9531 ref2_ p ref2_n 3.3v cmos c c r c r 1.2r ref3_ p ref3_n 3.3v cmos c 1.2r 73 74 62 63 1.8v 1.8v 12973-046 figure 47 . interfacing the ref2 or ref3 inputs to 3.3 v cmos choose the value of r and c in figure 47 based on the input frequency, f ref . typically, choose r to limit the current load on the cmos driver as given by r = 1.5/i load . then , choose c based on the input frequency such that c > 10/(r f ref ). the remaining shunt resistor is 1.2 the value of r and provides the necessary voltage scaling from 3.3 v to 1.8 v. for example, i load = 1 ma and f ref = 25 mhz results in r = 1.5 k (r shunt = 1.8 k ) and c > 270 pf . using ref2 or ref3 w ith a crystal resonator for applications using a crystal resonator as the reference input, the xtal amp lifier bit in the appropriate programming register must be set to logic 1. register 0x0200, bit d 4 applies to pll2 and register 0x0300, bit d 4 applies to pll3. figure 48 shows a typical crystal connection for both the pll2 and pll3 reference inputs. the internal input circuitry converts to an amplifier configuration to promote oscillation of the c rystal resonator. the value of the shunt capacitors (c) connecte d to the crystal depends on the crystal manufacturer load capacitance (c load ) specification for parallel resonance, as follows: c = 2 c load for example, a c load specification of 10 pf means t hat t he value of each of the two capacitors connected to the crystal is 20 pf. AD9531 ref2_ p c c ref2_n c c ref3_ p ref3_n 73 74 62 63 12973-047 figure 48 . interfacing the ref2 or ref3 inputs to a crystal resonator rev. 0 | page 87 of 88
AD9531 data sheet rev. 0 | page 88 of 88 outline dimensions * compliant to jedec standards mo-220-vrrd except for minimum thickness and lead count. 07-03-2014-c 1 22 66 45 23 44 88 67 0.50 0.40 0.30 0.30 0.23 0.18 10.50 ref 0.60 max 0.60 max 0.50 bsc 0.138~0.194 ref 12 max seating plane 0.70 0.65 0.60 0.045 0.025 0.005 pin 1 indicator 12.10 12.00 sq 11.90 11.85 11.75 sq 11.65 * 0.90 0.85 0.75 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 6.80 6.70 sq 6.60 pin 1 indicator top view exposed pad bottom view pkg-004081 figure 49. 88-lead lead frame chip scale package [lfcsp_vq] 12 mm 12 mm body, very thin quad (cp-88-5) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9531bcpz ?40c to +85c 88-lead lead frame chip scale package (lfcsp_vq) cp-88-5 AD9531bcpz-reel7 ?40c to +85c 88-lead lead frame chip scale package (lfcsp_vq) cp-88-5 AD9531/pcbz evaluation board 1 z = rohs compliant part. ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12973-0-1/16(0)

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